J.-F. de Marneffe

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Imaging performance of the EUV alpha semo tool at IMEC

Extreme Ultraviolet Lithography (EUVL) is the leading candidate beyond 32nm half-pitch device manufacturing. Having completed the installation of the ASML EUV full-field scanner, IMEC has a fully-integrated 300mm EUVL process line. Our current focus is on satisfying the specifications to produce real devices in our facilities. This paper reports on the imaging fingerprint of the EUV Alpha Demo Tool (ADT), detailing resolution, imaging, and overlay performance. Particular emphasis is given to small pitch contact holes, which are a critical layer for advanced manufacturing nodes and one of the most likely layers where EUVL may take over from 193nm lithography. Imaging of contact holes, pattern transfer and successful printing of the contact hole level on a 32nm SRAM device is demonstrated. The impact of flare and shadowing on EUV ADT performance is characterized experimentally, enabling the implementation of appropriate mitigation strategies.

A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond

Limits to the lithography process window restrict the scaling of critical IC features such as holes (contact, via) and trenches (required for interconnects and double patterning applications). To overcome this problem, contacts or trenches can be oversized during the exposure, followed by the application of a shrink technique. In this work, a novel shrink process utilizing plasma-assisted polymer deposition is demonstrated: a polymer is deposited on the top and sidewalls of photoresist by alternating deposition and etch steps, reducing the dimension of the lithography pattern in a controlled way. Hence very small patterns can be defined with wide process latitudes. This approach is generic and has been applied to both contacts and trenches. The feasibility of the plasma-assisted shrink technique was evaluated through extensive SEM inspections after lithography, after shrink, and after etch, as well as through electrical evaluations.

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the MotifTM CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.

Alternative integration of ultralow-k dielectrics by template replacement approach

Replacement of sacrificial template by ultralow-k dielectric was studied as an alternative integration approach for Cu/low-k interconnect. Metallization structure was first formed by patterning a template material. After template removal, a spin-on porous low-k was deposited on the metal lines. Then, planarization of the excess low-k was performed by CMP. The proposed approach does solve the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous structures.

Optimized pore stuffing for enhanced compatibility with interconnect integration flow

Plasma processing of porous órgano-silicate Iowie dielectrics, following the damascene approach. remains one the biggest challenge for IC manufacturing. During low-k plasma etching. reactive radicals (O*, F* amongst others) and VUV penetrate easily into the porous low-k structure, reacting with Si-CH3 terminating bonds, ultimately turning the etched low-k hydrophilic and raising the integrated k-value beyond acceptable limits.

Study on metrology of ERU tuning in TCP reactor, using PVx2 sensor wafer

The effect of the transformer-coupled capacitive tuning (TCCT) parameter on the etch rate uniformity (ERU) in a high density plasma etch chamber was studied by the following means: blanket wafer experiments; tests on patterned wafers with 20-nm half-pitch BEOL interconnect trenches, created by spacer defined double patterning; and PlasmaVolt™ X2 (PVx2) sensor wafer experiments. Besides pure Ar and pure SF6 chemistries, several typical process chemistries of poly-Si and SiO2 etching were selected for study. It was shown that the ERU data (expressed as 3σ) were in good agreement for all the chemistries applied to both PVx2 and blanket SiO2 with different TCCTs. The ERU of blanket poly-Si, however, did not generally correlate well with the PVx2 data. Only Ar sputtering and Cl2/HBr–based processes showed a similar 3σ trend for both PVx2 and poly-Si. For the 20-nm half-pitch wafers, a study was performed on three separate etch steps with different chemistries, used for SiOC, BARC, and SiN etching. The critical dimension (CD) uniformity data was compared to the PVx2 results and demonstrated a good correlation in the first two cases. Based on these results, it was concluded that PVx2 is able to predict the behavior of the ion-assisted etch component in terms of uniformity, while spontaneous chemical reactions and/or ion-assisted polymer deposition could result in a substantial discrepancy between the actual ERU data and the PVx2 results. Finally, for materials that are typically etched using a dominant ion-assisted etch component, it was estimated that use of this PVx2-based method of ERU tuning may result in lot turn time savings of 80% when compared to single-use blanket wafer ERU tests.

The metal hard-mask approach for contact patterning

Within the metal hard-mask (MHM) approach for contact patterning, the SiO2:TiN and SiO2:Si3N4 etch selectivities have been studied for an Ar-C4F8-CO-based discharge in a dual-frequency capacitive coupled plasma (DFC-CCP) chamber, as a function of gas additives and driving 2 MHz power. It is found that the O2 addition does dramatically decrease the SiO2:TiN and SiO2:Si3N4 selectivities, while 2MHz power raises the SiO2:Si3N4 but decreases the SiO2:TiN. The observed selectivity result from a balance between the sputtering by inert ions and the growth of a passivating fluorocarbon film, which thickness and composition depends on the substrate nature. Selectivity is also influenced by species kinetics at the plasma-surface interface.

Toward successful integration of gap-filling ultralow-k dielectrics

The replacement of a sacrificial template by gap-filling ultralow-k dielectric is studied as an alternative integration approach for Cu/low-k interconnects. The low-k curing processes induce severe damage to metallization structures, leading to detrimental electrical performance. Cu lines are passivated by a PECVD SiCN layer. Optimal yield can be restored, and promising electrical performance is demonstrated. Film shrinkage leads to low-k delamination in the trenches. By using multiple spin coating followed by soft bake, void free gap-filling structure is achieved.

H2 plasma and neutral beam treatment of EUV photoresist

Optical lithography has given the semiconductor industry the chance to follow Moore’s law in scaling the transistor dimensions and consequently stacking them in a more dense way. However, for present sub 20 nm nanoscale patterns, which are reaching molecular dimensions; controlling the line edge and width roughness (LER/LWR) has become a key challenge. One way of reducing the roughness at photoresist level is the exposure of the organic substrate to a hydrogen plasma process in a post lithography step. Unfortunately, to this day, no clear understanding of the interaction of various plasma parameters with EUV resist substrates has been reported. In this work, two EUV resist platforms were exposed to an H2 plasma environment and H2 energetic neutrals only, by using a customized plasma reactor. The surface and bulk modifications of the photoresists have been evaluated by spectroscopic ellipsometry, Fourier transformed infrared spectroscopy and atomic force microscopy.