Werner Boullart

Effects of various plasma pretreatments on 193nm photoresist and linewidth roughness after etching

Among the pretreatment methods which are performed just after the lithographic process to minimize the roughness increase of 193nm photoresist during the subsequent etching processes, an in situ plasma pretreatment is the most cost effective. A HBr plasma pretreatment has proven quite effective and a few papers have described the mechanism. In an effort to understand further, the authors evaluated four plasma pretreatments using HBr, Ar, H2, or Cl2 gases and compared their results. Fourier transform infrared (FTIR) spectroscopy was performed for the investigation of the chemical changes effected by the plasma pretreatments. Cross-section scanning electron microscope (SEM) images were used to measure the photoresist film thickness, while top-down SEM images and an off-line program were used to determine linewidth roughness (LWR) changes for 70 and 80nm line features. They found two different types of roughness. The first type is a low-frequency roughness, which repeats about every 400nm and increases the L...

Investigation of etching and deposition processes of Cl2/O2/Ar inductively coupled plasmas on silicon by means of plasma–surface simulations and experiments

In this paper, a simulation method is described to predict the etching behaviour of Cl2/O2/Ar inductively coupled plasmas on a Si substrate, as used in shallow trench isolation for the production of electronic devices. The hybrid plasma equipment model (HPEM) developed by Kushner et al is applied to calculate the plasma characteristics in the reactor chamber and two additional Monte Carlo simulations are performed to predict the fluxes, angles and energy of the plasma species bombarding the Si substrate, as well as the resulting surface processes such as etching and deposition. The simulations are performed for a wide variety of operating conditions such as gas composition, chamber pressure, power deposition and substrate bias. It is predicted by the simulations that when the fraction of oxygen in the gas mixture is too high, the oxidation of the Si substrate is superior to the etching of Si by chlorine species, resulting in an etch rate close to zero as is also observed in the experiments.

SELECTIVE REMOVAL OF HIGH-K GATE DIELECTRICS

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. First, the fundamentals and limitations of both approaches are presented, then an overview of the existing experimental data is given. It is concluded that the best results could be obtained by combining the dry and wet approaches.

Effect of energetic ions on plasma damage of porous SiCOH low-k materials

Plasma damage of SiCOH low-k films in an oxygen plasma is studied using a transformer coupled plasma reactor. The concentration of oxygen atoms and O2+ ions is varied by using three different conditions: (1) bottom power only, (2) bottom and top power, and (3) top power only. After plasma exposure, the low-k samples are characterized by various experimental techniques. It is shown that the ion bombardment induced by the bottom power minimizes the plasma damage by increasing the recombination coefficient of oxygen radicals. Contrary to the expectations, the densification of the top surface by ion radiation was limited. The increase in the recombination coefficient is mainly provided by modification of the pore wall surface and creation of chemically active sites stimulating the recombination of oxygen atoms. The results show that a reduction in plasma damage can be achieved without sealing of low-k top surface.

Simulation of an Ar/Cl2 inductively coupled plasma: study of the effect of bias, power and pressure and comparison with experiments

A hybrid model, called the hybrid plasma equipment model, was used to study Ar/Cl2 inductively coupled plasmas used for the etching of Si. The effects of substrate bias, source power and gas pressure on the plasma characteristics and on the fluxes and energies of plasma species bombarding the substrate were observed. A comparison with experimentally measured etch rates was made to investigate how the etch process is influenced and which plasma species mainly account for the etch process. First, the general plasma characteristics are investigated at the following operating conditions: 10% Ar 90% Cl2 gas mixture, 5 mTorr total gas pressure, 100 sccm gas flow rate, 250 W source power, −200 V dc bias at the substrate electrode and an operating frequency of 13.56 MHz applied to the coil and to the substrate electrode. Subsequently, the pressure is varied from 5 to 80 mTorr, the substrate bias from −100 to −300 V and the source power from 250 to 1000 W. Increasing the total gas pressure results in a decrease of the etch rate and a less anisotropic flux to the substrate due to more collisions of the ions in the sheath. Increasing the substrate bias has an effect on the energy of the ions bombarding the substrate and to a lesser extent on the magnitude of the ion flux. When source power is increased, it was found that, not the energy, but the magnitude of the ion flux is increased. The etch rate was more influenced by a variation of the substrate bias than by a variation of the source power, at these operating conditions. These results suggest that the etch process is mainly affected by the energy of the ions bombarding the substrate and the magnitude of the ion flux, and to a lesser extent by the magnitude of the radical flux.

Modeling Cl2/O2/Ar inductively coupled plasmas used for silicon etching: effects of SiO2 chamber wall coating

In this paper, simulations are performed to gain a better insight into the properties of a Cl2/Ar plasma, with and without O2, during plasma etching of Si. Both plasma and surface properties are calculated in a self-consistent manner. Special attention is paid to the behavior of etch products coming from the wafer or the walls, and how the chamber walls can affect the plasma and the resulting etch process. Two modeling cases are considered. In the first case, the reactor walls are defined as clean (Al2O3), whereas in the second case a SiO2 coating is introduced on the reactor walls before the etching process, so that oxygen will be sputtered from the walls and introduced into the plasma. For this reason, a detailed reaction set is presented for a Cl2/O2/Ar plasma containing etched species, as well as an extensive reaction set for surface processes, including physical and chemical sputtering, chemical etching and deposition processes. Density and flux profiles of various species are presented for a better understanding of the bulk plasma during the etching process. Detailed information is also given on the composition of the surfaces at various locations of the reactor, on the etch products in the plasma and on the surface loss probabilities of the plasma species at the walls, with different compositions. It is found that in the clean chamber, walls are mostly chlorinated (Al2Cl3), with a thin layer of etch products residing on the wall. In the coated chamber, an oxy-chloride layer is grown on the walls for a few nanometers during the etching process. The Cl atom wall loss probability is found to decrease significantly in the coated chamber, hence increasing the etch rate. SiCl2, SiCl4 and SiCl3 are found to be the main etch products in the plasma, with the fraction of SiCl2 being always slightly higher. The simulation results compare well with experimental data available from the literature.

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V/sub T/ of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I/sub on/-I/sub off/ of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V/sub D/=l .3V for an EOT of 1.8nm.

Silicon Nano-Pillar Test Structures for Quantitative Evaluation of Wafer Drying Induced Pattern Collapse

Silicon nano-pillars as test structures for quantitative evaluation of advanced wafer drying are presented. The method consists of the use of pillar structures with an aspect ratio up to 28 in combination with top-down SEM inspection and subsequent image analysis for quantification. The test vehicle allows characterizing cleaning techniques by a threshold aspect ratio below which value the features do not collapse. As such, a higher critical aspect ratio corresponds to a superior wetting/drying method. Furthermore, as the metrology is specific and includes cluster size distribution analysis, it can bring new insights in the mechanism of pattern collapse.

45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/m

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

Profile control of novel non-Si gates using BCl3∕N2 plasma

The authors found that a BCl3∕N2 plasma is very suitable for metal gate patterning and profile control as it produces a passivating film during the etching. On blanket wafers, a boron-nitride-like film is deposited from a boron trichloride/nitride plasma mixture in a standard etch chamber at temperatures as low as 60°C. Deposition rate can be varied from 10 to more than 100nm∕min depending on the plasma conditions and BCl3∕N2 ratio. The film contains hexagonal boron nitride but is very unlikely to be a stoichiometric BN. It decomposes at elevated temperatures and is water soluble. The latter property makes the postetch clean relatively straightforward. This film can be used for sidewall passivation during the patterning of advanced non-Si gates, e.g., metal gates. They are presenting the use of BCl3∕N2 plasma for patterning of Ge and TaN gates as examples. The Ge gate profile is damaged by a pure BCl3 plasma during high-k dielectric (HfO2) etching after the gate patterning. Addition of 10% N2 to the BCl3 ...