J.F. Duque-Carrillo

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output.

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-/spl mu/m CMOS process. Experimental results are provided and the corresponding performances are discussed and compared.

Am improved tail current source for low voltage applications

A new current source for low-voltage applications is proposed. This current source is well suited for biasing differential pairs and source followers. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured to be 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully balanced and single-ended differential amplifiers.

Cork quality classification system using a unified image processing and fuzzy-neural network methodology

Cork is a natural material produced in the Mediterranean countries. Cork stoppers are used to seal wine bottles, Cork stopper quality classification is a practical pattern classification problem. The cork stoppers are grouped into eight classes according to the degree of defects on the cork surface. These defects appear in the form of random-shaped holes, cracks, and others. As a result, the classification cork stopper is not a simple object recognition problem. This is because the pattern features are not specifically defined to a particular shape or size. Thus, a complex classification form is involved, Furthermore, there is a need to build a standard quality control system in order to reduce the classification problems in the cork stopper industry. The solution requires factory automation meeting low time and reduced cost requirements. This paper describes a cork stopper quality classification system using morphological filtering and contour extraction and following (CEF) as the feature extraction method, and a fuzzy-neural network as a classifier. This approach will be used on a daily basis. A new adaptive image thresholding method using iterative and localized scheme is also proposed, A fully functioning prototype of the system has been built and successfully tested. The test results showed a 6.7% rejection ratio, It is compared with the 40% counterpart provided by traditional systems. The human experts in the cork stopper industry rated this proposed classification approach as excellent.

An improved current source for low voltage applications

A new current source which is well suited for low voltage applications is proposed. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured at 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully-balanced and single-ended differential amplifiers.

VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications

A CMOS mixed-mode fully-differential signal processor (VERDI), that constitutes the core of a hearing aid system, is introduced. Its characteristics (frequency response, compression level, and output sound pressure level) are wireless controlled by means of dual tone multi-frequency (DTMF) encoded signals transmitted by an external unit. A system description is provided, and the implementation and experimental results of the key components (preamplifier, antialiasing filter, automatic gain control, filter section, output amplifier, and DTMF receiver/decoder) are covered in more detail. The circuit has been fabricated in a conventional 1.2 /spl mu/m CMOS n-well process and operates from a single 1.3 V battery, although a dc/dc converter is required. It consumes typically less than 1 mA and occupies 28 mm/sup 2/ of silicon. The dynamic range is larger than 66 dB for the maximum input signal (54 mV/sub rms/=108 dB SPL).

Constant-G/sub m/ rail-to-rail common-mode range input stage with minimum CMRR degradation

The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2- mu m feature size are given. >

Biasing circuit for high input swing operational amplifiers

This paper introduces a biasing scheme that overcomes the inherent drawbacks associated with high input common-mode range (CMR) amplifiers: nonconstant transconductance (G/sub m/) and very poor common-mode rejection ratio (CMRR). The proposed circuit achieves a constant amplifier G/sub m/ by maintaining a constant sum of the square-roots of the bias currents of the complementary input pairs, while the high rejection to input common-mode signals is achieved by making a gradual transition between these currents as function of the input common-mode component (V/sub m, cm/). Experimental results obtained from a CMOS n-well 2 /spl mu/m chip prototype with 5 V of total supply voltage, show a maximum transconductance deviation less than 5% from its value for a common-mode input voltage at midsupply, as well as a CMRR improvement of 12 dB with respect to the classical biasing scheme. Other representative figures of its experimental behavior are also given. >

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed scheme provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, whilst imposing no appreciable constraint for high-frequency operation. In addition, the technique does not rely on any strict matching condition between complementary differential pairs, and is compatible with deep submicron CMOS devices, where the familiar voltage-to-current square-law in saturation is not completely satisfied. Experimental results on integrated prototypes are provided.

Programmable switched-capacitor bump equalizer architecture

A versatile and economical switched-capacitor (SC) equalizing structure to compensate attenuation characteristics is presented. The monolithic SC bump equalizer has three operational amplifiers and six capacitor banks to independently control the center frequency, bandwidth, and peak voltage gain steps for the bump (and dip) frequency response. The bump equalizer has been integrated using 3- mu m CMOS (p-well) technology and occupies an area of 3.36 mm/sup 2/, including an additional test amplifier and test buffer. The circuit operating from +or-5-V power supplies typically dissipates 60 mW when sampled at 75 kHz. >