J.M. Valverde

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-/spl mu/m CMOS process. Experimental results are provided and the corresponding performances are discussed and compared.

Cork quality classification system using a unified image processing and fuzzy-neural network methodology

Cork is a natural material produced in the Mediterranean countries. Cork stoppers are used to seal wine bottles, Cork stopper quality classification is a practical pattern classification problem. The cork stoppers are grouped into eight classes according to the degree of defects on the cork surface. These defects appear in the form of random-shaped holes, cracks, and others. As a result, the classification cork stopper is not a simple object recognition problem. This is because the pattern features are not specifically defined to a particular shape or size. Thus, a complex classification form is involved, Furthermore, there is a need to build a standard quality control system in order to reduce the classification problems in the cork stopper industry. The solution requires factory automation meeting low time and reduced cost requirements. This paper describes a cork stopper quality classification system using morphological filtering and contour extraction and following (CEF) as the feature extraction method, and a fuzzy-neural network as a classifier. This approach will be used on a daily basis. A new adaptive image thresholding method using iterative and localized scheme is also proposed, A fully functioning prototype of the system has been built and successfully tested. The test results showed a 6.7% rejection ratio, It is compared with the 40% counterpart provided by traditional systems. The human experts in the cork stopper industry rated this proposed classification approach as excellent.

VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications

A CMOS mixed-mode fully-differential signal processor (VERDI), that constitutes the core of a hearing aid system, is introduced. Its characteristics (frequency response, compression level, and output sound pressure level) are wireless controlled by means of dual tone multi-frequency (DTMF) encoded signals transmitted by an external unit. A system description is provided, and the implementation and experimental results of the key components (preamplifier, antialiasing filter, automatic gain control, filter section, output amplifier, and DTMF receiver/decoder) are covered in more detail. The circuit has been fabricated in a conventional 1.2 /spl mu/m CMOS n-well process and operates from a single 1.3 V battery, although a dc/dc converter is required. It consumes typically less than 1 mA and occupies 28 mm/sup 2/ of silicon. The dynamic range is larger than 66 dB for the maximum input signal (54 mV/sub rms/=108 dB SPL).

Constant-G/sub m/ rail-to-rail common-mode range input stage with minimum CMRR degradation

The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2- mu m feature size are given. >

Biasing circuit for high input swing operational amplifiers

This paper introduces a biasing scheme that overcomes the inherent drawbacks associated with high input common-mode range (CMR) amplifiers: nonconstant transconductance (G/sub m/) and very poor common-mode rejection ratio (CMRR). The proposed circuit achieves a constant amplifier G/sub m/ by maintaining a constant sum of the square-roots of the bias currents of the complementary input pairs, while the high rejection to input common-mode signals is achieved by making a gradual transition between these currents as function of the input common-mode component (V/sub m, cm/). Experimental results obtained from a CMOS n-well 2 /spl mu/m chip prototype with 5 V of total supply voltage, show a maximum transconductance deviation less than 5% from its value for a common-mode input voltage at midsupply, as well as a CMRR improvement of 12 dB with respect to the classical biasing scheme. Other representative figures of its experimental behavior are also given. >

Fully differential basic building blocks based on fully differential difference amplifiers with unity-gain difference feedback

A set of truly fully differential (FD) basic building blocks is presented. They are based on differential difference amplifiers with differential output (FDDA, fully differential difference amplifier) in unity gain difference feedback configuration. Simulation results at the transistor level demonstrate their suitability for FD signal processing. >

Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations

A time-multiplexed digitally-programmable switched-capacitor (SC) variable equalizer which allows the realization of arbitrary frequency responses is presented. The circuit performs the same operation as a cascade of N second-order programmable equalizers, where N is also the multiplexing order. Except the storing capacitors, the rest of the circuitry is shared for all individual equalizer functions (channels), resulting in silicon area savings higher than 60% with respect to a direct circuit implementation for N=4. The impact on circuit performance of crosstalk effects is discussed. Experimental results of a 3-V timesharing SC equalizer architecture fabricated in a CMOS 1.2 /spl mu/m technology are given for different values of the multiplexing order. The circuit has been designed to be incorporated in a programmable hearing aid device.

A family of bias circuits for high input swing CMOS operational amplifiers

A set of three circuits for biasing CMOS amplifiers with rail-to-rail input common-mode range is presented. By controlling the bias current levels, they avoid the large magnitude deviations inherent in these amplifiers with composite input pairs. The deviations are with regard to their value for input voltages in the mid-range between supplies. Thus, the optimization and compensation is facilitated, as well as an increase in the common-mode rejection ratio (CMRR) over 17 dB in comparison to the classical biasing schemes.<<ETX>>

Common-mode response shaping in rail-to-rail op-amp input stages

Low-voltage rail-to-rail (r-t-r) operational amplifiers (op-amps) suffer from large deviations in their small-signal and large signal behaviors, as a function of the input common-mode (CM) voltage. This paper introduces the concept of the CM response shaping as an effective technique for maintaining roughly constant op-amp behaviors over the full input range. This is achieved by means of two input variable floating voltage sources. Experimental results obtained from a 0.8-/spl mu/m standard CMOS 3-V input/output r-t-r op-amp are shown.

A class of fully-differential basic building blocks based on unity-gain difference feedback

A set of truly fully-differential (FD) basic building blocks is presented. They are based on differential difference amplifiers with differential output (FDDA, fully-differential difference amplifier) in unity-gain difference feedback configuration. Simulation results at the transistor level demonstrate their suitability for FD signal processing.