J.F. Lopez

Performance Evaluation of the H.264/AVC Video Coding Standard for Lossy Hyperspectral Image Compression

In this paper, a performance evaluation of the state-of-the-art H.264/AVC video coding standard is carried out with the aim of determining its feasibility when applied to hyperspectral image compression. Results are obtained based on configuring diverse parameters in the encoder in order to achieve an optimal trade-off between compression ratio, accuracy of unmixing and computation time. In this sense, simulations are developed in order to measure the spectral angles and signal-to-noise ratio (SNR), achieving compression ratios up to 0.13 bits per pixel per band (bpppb) for real hyperspectral images. Moreover, in this work it is detected which blocks in the encoder contribute the most to performance improvements of the compression task for the particular case of this type of images, and which ones are not relevant at all and hence could be removed. This conclusion yields to reduce the future design complexities of potential low-power/real-time hyperspectral encoders based on H.264/AVC for remote sensing applications.

A Novel Architecture for Hyperspectral Endmember Extraction by Means of the Modified Vertex Component Analysis (MVCA) Algorithm

There is presently a high interest in the spatial industry to develop high-performance on-board processing platforms with a high degree of flexibility, so they can adapt to varying mission needs and/or to future space standards. For this purpose, Field Programmable Gate Array (FPGA) devices have demonstrated to offer an excellent compromise between flexibility and performance. This work presents a novel FPGA-based architecture to be used as part of the hyperspectral linear unmixing processing chain. In particular, this paper introduces a new architecture for hyperspectral endmember extraction accordingly to the Modified Vertex Component Analysis (MVCA) algorithm, which provides a better figure of merit in terms of endmember extraction accuracy versus computational complexity than the Vertex Component Analysis (VCA) algorithm. Two versions of the MVCA algorithm which differ on the use of floating point or integer arithmetic for iteratively projecting the hyperspectral cube onto a direction orthogonal to the subspace spanned by the endmembers already computed have been mapped onto a Xilinx Virtex-5 FPGA. The results demonstrate that both versions are capable of processing hyperspectral images captured by the NASAs AVIRIS sensor in real-time, showing the latter a better performance in terms of hardware resources and processing speed. Furthermore, our proposal constitutes the first published architecture for extracting the endmembers from a hyperspectral image based on the VCA principle and thus, it provides a basis for future FPGA implementations of state-of-the-art hyperspectral algorithms with similar characteristics, such as the Automatic Target Generation Process (ATGP) or the Orthogonal Subspace Projection (OSP) algorithms.

Highly-Parallel GPU Architecture for Lossy Hyperspectral Image Compression

Graphics Processing Units (GPU) are becoming a widespread tool for general-purpose scientific computing, and are attracting interest for future onboard satellite image processing payloads due to their ability to perform massively parallel computations. This paper describes the GPU implementation of an algorithm for onboard lossy hyperspectral image compression, and proposes an architecture that allows to accelerate the compression task by parallelizing it on the GPU. The selected algorithm was amenable to parallel computation owing to its block-based operation, and has been optimized here to facilitate GPU implementation incurring a negligible overhead with respect to the original single-threaded version. In particular, a parallelization strategy has been designed for both the compressor and the corresponding decompressor, which are implemented on a GPU using Nvidias CUDA parallel architecture. Experimental results on several hyperspectral images with different spatial and spectral dimensions are presented, showing significant speed-ups with respect to a single-threaded CPU implementation. These results highlight the significant benefits of GPUs for onboard image processing, and particularly image compression, demonstrating the potential of GPUs as a future hardware platform for very high data rate instruments.

Parallel Implementation of the Modified Vertex Component Analysis Algorithm for Hyperspectral Unmixing Using OpenCL

Hyperspectral imaging represents the state-of-theart technique in those applications related to environmental monitoring, military surveillance, or rare mineral detection. However, one of the requirements of paramount importance when dealing with such scenarios is the ability to achieve real-time constraints taking into account the huge amount of data involved in processing this type of images. In this paper, the authors present for the first time a combination of the newly introduced modified vertex component analysis (MVCA) algorithm for the process of endmembers extraction together with the ability of GPUs to exploit its parallelism, giving, as a result, important speedup factors with respect to its sequential counterpart, while maintaining the same levels of endmember extraction accuracy than the vertex component analysis (VCA) algorithm. Furthermore, OpenCL ensures the use of generic computing platforms without being restricted to a particular vendor. The proposed approach has been assessed on a set of synthetic images as well as on the well-known Cuprite real image, showing that the most time-consuming operations are located on the matrix projection and the maximum search processes. Comparison of the proposed technique with a single-threaded C-based implementation of the MVCA algorithm shows a speedup factor of 8.87 for a 500 × 500 pixel artificial image with 20 endmembers and 7.14 for the wellknown Cuprite hyperspectral data set, including in both cases I/O transfers. Moreover, when the proposed implementation is compared with respect to a C-based sequential implementation of the VCA algorithm, a speedup of 115 has been achieved. In all the cases, the results obtained by the MVCA are the same as the ones obtained with the VCA; thus, the accuracy of the proposed algorithm is not compromised.

State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. High-performance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with significantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.

Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches

Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ scheduling algorithms, as exemplified by PIM and iSLIP, re based on parallel and iterative request-grant-accept arbitration schemes. Conventional performance evaluation of these scheduling algorithms, does not consider the effect of some issues inherent to their implementation on a modular and scalable VOQ switch with input ports and switch matrix residing on separate cards. One of the main issues is the Round-Trip Delay (RTD), defined as the latency between a connection is requested to the switch matrix card and the associated acceptance notification is received on the input port card. In this paper, the effect of RTD on performance parameters for PIM and iSLIP algorithms is presented, not being considered in deep in previous works appearing In the literature. Based on simulation results, RTD is demonstrated to affect significantly contention on output ports and mean queuing delay, and thus degrade the performance of cell-based VOQ switches.

GaAs pseudodynamic latched logic for high performance processor cores

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLAs), and carry lookahead adders (CLAs) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems.

Multispectral and Hyperspectral Lossless Compressor for Space Applications (HyLoC): A Low-Complexity FPGA Implementation of the CCSDS 123 Standard

An efficient compression of hyperspectral images on-board satellites is mandatory in current and future space missions in order to save bandwidth and storage space. Reducing the data volume in space is a challenge that has been faced with a twofold approach: to propose new highly efficient compression algorithms; and to present technologies and strategies to execute the compression in the hardware available on-board. The Consultative Committee for Space Data Systems (CCSDS), a consortium of the major space agencies in the world, has recently issued the CCSDS 123 standard for multispectral and hyperspectral image (MHI) compression, with the aim of facilitating the inclusion of on-board compression on satellites by the space industry. In this paper, we present a low-complexity feld programmable gate arrays (FPGAs) implementation of this recent CCSDS 123 standard, which demonstrates its main features in terms of compression efficiency and suitability for an implementation on the available on-board technologies. A hardware architecture is conceived and designed with the aim of achieving low hardware occupancy and high performance on a space-qualified FPGA from the Microsemi RTAX family. The resulting FPGA implementation is therefore suitable for on-board compression. The effect of the several CCSDS-123 configuration parameters on the compression efficiency and hardware complexity is taken into consideration to provide flexibility in such a way that the implementation can be adapted to different application scenarios. Synthesis results show a very low occupancy of 34% and a maximum frequency of 43 MHz on a space-qualified RTAX1000S. The benefits of the proposed implementation are further evidenced by a demonstrator, which is implemented on a commercial prototyping board from Xilinx. Finally, a comparison with other FPGA implementations of on-board data compression algorithms is provided.

Survey of reconfigurable architectures for multimedia applications

In a short period of time, the multimedia sector has quickly progressed trying to overcome the exigencies of the customers in terms of transfer speeds, storage memory, image quality, and functionalities. In order to cope with this stringent situation, different hardware devices have been developed as possible choices. Despite of the fact that not every device is apt for implementing the high computational demands associated to multimedia applications; reconfigurable architectures appear as ideal candidates to achieve these necessities. As a direct consequence, worldwide universities and industries have incremented their research activity into this area, generating an important know-how base. In order to sort all the information generated about this issue, this paper reviews the most recent reconfigurable architectures for multimedia applications. As a result, this paper establishes the benefits and drawbacks of the different dynamically reconfigurable architectures for multimedia applications according to their system-level design.

Low-cost implementation of a super-resolution algorithm for real-time video applications

In this paper, a novel algorithm based on superresolution (SR) techniques for increasing the quality of video sequences, is presented together with its mapping into the Philips Research proprietary hardware-software platform. As result, a low-cost real-time implementation is obtained, suitable for personal multimedia applications. Low cost constraints are accomplished by re-using a video codec: and introducing some changes in order to avoid the use of specific SR hardware. As a consequence, a drastic reduction in the memory requirements is obtained at the expense of less than a 7% quality loss with respect to previous works.