F. Tobajas

An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented. The deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both the encoding and decoding processes. The proposed architecture is based on a double- filter strategy that results in a significant saving in filtering cycles, memory requirements and gate count when compared with state-of-the-art approaches. The proposed architecture is implemented in synthesizable HDL at RTL level and verified with the reference software. This hardware is designed to be used as part of a complete H.264/A VC video coding system.

Low cost efficient architecture for H.264 motion estimation

A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the power dissipation. As result, the implementation of the architecture in a low cost commercial FPGA is outlined in this paper, showing characteristics such as a reduced area occupation and an appropriate range of operation frequencies that make the architecture suitable for portable multimedia devices.

A novel real-time DSP-based video super-resolution system

The possibility of increasing the spatial resolution of video sequences is becoming extremely important in present-day multimedia systems. In this sense, super-resolution represents a smart way to obtain high-resolution video sequences from a finite set of low-resolution video frames. This set of low-resolution images must be obtained under different capture conditions of the image, from different spatial positions and/or from different cameras - this being the super-resolution paradigm, which is one of the fundamental challenges of sensor fusion. However, the vast computational cost associated with common super-resolution techniques jeopardizes their usefulness for real-time consumer applications. To alleviate this drawback, an implementation of a proprietary super-resolution algorithm mapped onto a hardware platform based on a digital signal processor (DSP) is presented in this paper. The results obtained show that, after an incremental optimization procedure, we are able to obtain super-resolved CIF video sequences (352 × 288 pixels) at 38 frames per second.

Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches

Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ scheduling algorithms, as exemplified by PIM and iSLIP, re based on parallel and iterative request-grant-accept arbitration schemes. Conventional performance evaluation of these scheduling algorithms, does not consider the effect of some issues inherent to their implementation on a modular and scalable VOQ switch with input ports and switch matrix residing on separate cards. One of the main issues is the Round-Trip Delay (RTD), defined as the latency between a connection is requested to the switch matrix card and the associated acceptance notification is received on the input port card. In this paper, the effect of RTD on performance parameters for PIM and iSLIP algorithms is presented, not being considered in deep in previous works appearing In the literature. Based on simulation results, RTD is demonstrated to affect significantly contention on output ports and mean queuing delay, and thus degrade the performance of cell-based VOQ switches.

Survey of reconfigurable architectures for multimedia applications

In a short period of time, the multimedia sector has quickly progressed trying to overcome the exigencies of the customers in terms of transfer speeds, storage memory, image quality, and functionalities. In order to cope with this stringent situation, different hardware devices have been developed as possible choices. Despite of the fact that not every device is apt for implementing the high computational demands associated to multimedia applications; reconfigurable architectures appear as ideal candidates to achieve these necessities. As a direct consequence, worldwide universities and industries have incremented their research activity into this area, generating an important know-how base. In order to sort all the information generated about this issue, this paper reviews the most recent reconfigurable architectures for multimedia applications. As a result, this paper establishes the benefits and drawbacks of the different dynamically reconfigurable architectures for multimedia applications according to their system-level design.

A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology

In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technologys corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation

A flexible template for H.264/AVC block matching motion estimation architectures

Motion estimation architectures play a fundamental role in nowadays real time video encoding systems. However, in spite of their relevance, the influence of the allocation of the computing resources in terms of the final area, power dissipation and processing speed of such architectures has not been studied in depth in the recent literature. In this sense, a new approach for exploring different allocation alternatives of the computational resources within H.264/AVC block matching motion estimation architectures is presented in this paper. In particular, a novel architectural template is introduced allowing the establishment, in a highly flexible way, of different groups of processing elements (PEs) within one-dimensional motion estimation arrays. The use of this methodology has enabled the evaluation of different design tradeoffs, motivating the introduction of a new architecture composed of four independents groups with four PEs each, able to process CIF@60fps sequences with a reduced equivalent gate count and dynamic power savings.

Super-resolution with adaptive macro-block topology applied to a multi-camera system

Super-Resolution (SR) consists in processing an image or a set of images in order to enhance the resolution of a video sequence or a single frame. In this paper, fusion SR techniques are considered, where High-Resolution (HR) images are constructed from several observed Low-Resolution (LR) images, thereby increasing the high-frequency components and removing the degradations caused by the recording process of LR imaging acquisition devices. This paper follows a strategy combining the selection of the most appropriate frames and adaptive sized Macro-Blocks (MBs) together with a Multi-Camera (MC) system. This proposal optimizes the spatial and temporal correlations between the recorded sequences, and minimizes the appearance of annoying artifacts at the same time, improving the quality of the super-resolved HR sequence and reducing the computational cost by more than a factor of two. This type of image enhancement systems has many applications in Consumer Electronics appliances related to imaging. More specifically, many camera suppliers are incorporating Super-Resolution in their high-end products.

Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution

Nowadays, images are employed in several areas of medicine for early diagnosis. In this sense, the industry provides accurate models to obtain, for example, X-ray and cardiology images of high resolution. However, other images, such as those related to pathological anatomy present in many situations poor quality, which complicates the diagnostic process. This work is focused on the quality enhancement of this type of images through a system based on super-resolution techniques. The results show that the proposed methodology can help medical specialists in the diagnostic of several pathologies.

A 600 MHz 2D-DCT processor for MPEG applications

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.