Valentín de Armas

Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution

Nowadays, images are employed in several areas of medicine for early diagnosis. In this sense, the industry provides accurate models to obtain, for example, X-ray and cardiology images of high resolution. However, other images, such as those related to pathological anatomy present in many situations poor quality, which complicates the diagnostic process. This work is focused on the quality enhancement of this type of images through a system based on super-resolution techniques. The results show that the proposed methodology can help medical specialists in the diagnostic of several pathologies.

A 600 MHz 2D-DCT processor for MPEG applications

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.

Hardware platform for wide-area vehicular sensor networks with mobile nodes

In recent years, Wireless Sensor Networks have experienced significant growth, mainly motivated by the development of standard communication protocols and the availability of low cost microcontrollers and wireless transceivers, resulting in low-power small-size sensing and data processing capable devices, and wireless communication links. In this paper, a hardware platform for the deployment of a heterogeneous multi-tiered Sensor Network architecture supporting highly mobile nodes covering wide geographic areas for automotive applications is proposed. In the presented network architecture, the low level system consists of an IEEE 802.15.4 based Wireless Sensor Network fully composed of compatible devices that support all the standard functionalities. As a novelty, some extensions are proposed to release part of the topological restrictions of IEEE 802.15.4 communication protocol which limit the development of WSN for applications with wide area coverage and high mobility requirements. The proposed hardware platform has been implemented and experimentally validated and characterized in vehicular applications to monitor and communicate specific environmental parameters in a heavy transport fleet.

Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform

MultiProcessor Systems-on-Chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. For that purpose, Networks-on-Chip (NoC) are proposed as a promising solution to interconnection in MPSoCs for reasons of efficiency and scalability. In this scenario, the need to develop low-cost platforms to support NoC-based SoC design and verification is growing. In this work, the design of a low cost NoC-based MPSoC platform and its application to a video enhancement algorithm based on Super Resolution (SR) are presented. To validate the designed hardware platform, an optimized SR algorithm is mapped on the Processing Elements (PE) of the NoC-based SoC platform. Finally, the performance is characterized from experimental measurements according to the type of application, as well as the number of PE used.

Network-on-chip emulation framework for multimedia SoC development

Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is designed and implemented on a low-cost FPGA device. The objective of this work is the design and implementation of a prototyping platform with NoC topology, which provides a demonstrator for the implementation of multimedia applications. The emulation platform will allow evaluation, comparison, and verification of different aspects of a NoC design for SoCs intended for the execution of multimedia applications. The proposed emulation platform consists of different type of functional IP blocks (microprocessors, memory blocks, peripherals, additional blocks, etc.) interconnected through an interconnection infrastructure based on NoC. In order to provide a low-cost solution, the platform design is restricted to use a single FPGA, resulting in a low-scale SoC due to the limited resources available in the FPGA used. However, the proposed design may be scalable and replicate in large scale FPGA or multi-FPGA devices to increase emulation performance. In this work, a design flow, which integrates different commercial EDA tools, is presented, and integration process is discussed in detail due to problems experienced in this stage. The platform is fully implemented on a Xilinx Spartan-6 LX45T FPGA and special attention is given to verification and floorplanning stages. Finally, various multimedia applications with real-time requirements are executed on the NoC-based SoC platform. At this stage, the performance results are analyzed according to the type of application, as well as the number of processors required.

Effectiveness of a peer mentoring program in engineering education

The Mentoring Program of the Escuela Técnica Superior de Ingenieros de Telecomunicación (ETSIT) is intended to establish a mechanism based on peer mentoring provided by upper-class students (Mentors) to provide help, support, and resources to incoming first-year students (Mentees). This paper focuses on the experience gained in the creation and development of the ETSIT Mentoring Program during five years. The evolution of the results obtained from the evaluation of various aspects of the ETSIT Mentoring Program, is also presented.

Supporting students with special needs at university through peer mentoring

This contribution focuses on the experience gained in the adaptation of a peer mentoring program to effectively provide support for students with special needs, and in particular for engineering students with Aspergers Syndrome (AS) at university. A detailed description of the program after two years of existence is provided, including the specific needs of the participant students, as well as its objectives, structure, and implementation. The results from the ongoing evaluation of the effectiveness and success of the program are also presented.

Wireless sensor network for wide-area high-mobility applications

In recent years, IEEE 802.15.4-based Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by the standard features, such as small size oriented devices, low power consumption nodes, wireless communication links, and sensing and data processing capabilities. In this paper, the development, implementation and deployment of a novel fully compatible IEEE 802.15.4-based WSN architecture for applications operating over extended geographic regions with high node mobility support, is described. In addition, a practical system implementation of the proposed WSN architecture is presented and described for experimental validation and characterization purposes.

Evaluation of a peer Mentoring Program by Mentees after staying three years at the university

Though Peer Mentoring is often cited as among the most influential factors on retention rates and degree completion, that influence is difficult to assess. From the academic year 2007- 2008, the evaluation of the Mentoring Program of the Escuela Técnica Superior de Ingenieros de Telecomunicación (PM-ETSIT) at the University of Las Palmas de Gran Canaria (ULPGC), which is currently in its seventh year of operation, involves as a differential factor a complementary evaluation based on specific satisfaction surveys completed by Mentees after staying three years at the University. In this paper, the results obtained from the appraisal of the influence of the PM-ETSIT in different aspects of the students academic life, including their decision to remain at the University, are presented.

NoC emulation framework based on Arteris NoC solution for multiprocessor system-on-chip

The growth of complexity and the requirements of on-chip technologies create the need for new architectures which generate solutions representing a compromise between complexity and power consumption, and Quality of Service (QoS) of the communications between the cores of a System-on-Chip (SoC). Network-on-Chip (NoC) arises as a solution to implement efficient interconnections in SoC. This new technology, due to its complexity, creates the need of specialized engineers who can design the intricate circuits that NoC requires. It is possible to reduce those specialization needs by using CAD tools. In this paper, one of this tools, called Arteris NoC Solution, is used for developing the proposed framework for NoC emulation. This software includes three different tools: NoCexplorer, for high-level simulation of an abstract model of the NoC, NoCcompiler, in which the NoC is defined and generated in HDL language, and NoCverifier, which performs simulations of the HDL code. Furthermore, a validation and characterization infrastructure was developed for the created NoC, which can be completely emulated in FPGA. This environment is composed by OCP traffic generators and receptors, which also can perform measurements over the created traffic, and a store and communication module, which is responsible for storing the results obtained from the emulation of the entire system in the FPGA, and send it to a PC. Once the data is stored in the PC, statistical analyses are performed, including a comparison of mean latency from high level simulations, RTL simulations and FPGA emulations. The analysis of the results is obtained from three scenarios with different NoC topologies for the same SoC design.