J.F. Verweij

Incubation time measurements in thin-film deposition

Studies on the initial growth or nucleation of materials and research on selective deposition often mention an incubation time. Many techniques exist to determine the incubation time. The outcome can be very different for each technique when the same nucleation process is considered. For the first time we have given a simple model which shows that several incubation times can be expected if different methods are used. One of the most popular methods, plotting the mass or thickness as a function of time and defining the incubation time as the intercept on the x-axis, is not a good method. In particular, a meaningful incubation time is found only if a layer-by-layer growth mechanism occurs right from the start. Ellipsometry can be used in situ and is a much more sensitive method, but this technique needs more research to correlate the nucleation process with the data obtained using this technique. The determination of the nucleus density using scanning electron microscopy or atomic force microscope is the most accurate method, yet needs a lot of experiments. Without a detailed description of the measurement method the incubation time is a meaningless quantity.

AN EMPIRICAL MODEL FOR EARLY RESISTANCE CHANGES DUE TO ELECTROMIGRATION

A new heuristic description for electromigration-induced early resistance changes is given. The basis is formed by two coupled partial differential equations, one for vacancies, and one for imperfections. These equations are solved numerically for a grain boundary bamboo structure. It is shown that this model is capable of simulating the typical effects as observed in early resistance change measurements. These early resistance changes are due to the redistributions of the vacancies and the generation of imperfections. Simulations are performed that closely match the measured resistance change curves.

Electrical breakdown of amorphous hydrogenated silicon rich silicon nitride thin film diodes

Electrical breakdown, both intrinsic and extrinsic, of thin film diodes used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, thermal measurements, thermal 3D simulations, electrical simulations and post breakdown observations. The diodes used in this study consist of a layer of 30 nm amorphous hydrogenated silicon rich silicon nitride, sandwiched between metal electrodes. It will be shown that breakdown under dc bias is a thermal process. Thermal breakdown is shown to occur above a temperature level of 234/spl deg/C and is triggered by the onset of hydrogen effusion. Under certain conditions, low ohmic links are formed as a result of breakdown. Breakdown due to very short pulses (50-500 ns) shows a remarkable asymmetry in breakdown current between polarities. A hypothesis on this asymmetry is presented. Measurements suggest that a relation exists between current flow induced state creation in the nitride and breakdown phenomena. Furthermore, a statistical measurement technique is presented that uses breakdown to monitor the switch reliability in active matrix LCD production.

Dielectric breakdown II: Related projects at the University of Twente

In this paper an overview is given of the related activities in our group of the University of Twente. These are on thin film transistors with the inherent difficulty of making a gate dielectric at low temperature, on thin dielectrics for EEPROM devices with well-known requirements with respect to charge retention and endurance and, finally, on thin film diodes in displays with unexpected breakdown properties.

Comprehensive physical modeling of NMOSFET hot-carrier-induced degradation

The role of hot-carrier-induced interface states in NMOSFETs is discussed. A new model is proposed based on measurements in several 0.7/spl mu/m CMOS technologies of different suppliers. Our model for the first time enables accurate interface state prediction over many orders of magnitude in time for all stress conditions under pinch-off and incorporates saturation. It can easily be implemented in a reliability circuit simulator, enabling more accurate NMOSFET parameter degradation calculations (e.g. /spl Delta/I/sub D/, /spl Delta/g/sub m/ etc.).