Jinsu Yoon

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 105 times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 105 with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density.

Pattern Recognition Using Carbon Nanotube Synaptic Transistors with an Adjustable Weight Update Protocol

Recent electronic applications require an efficient computing system that can perform data processing with limited energy consumption. Inspired by the massive parallelism of the human brain, a neuromorphic system (hardware neural network) may provide an efficient computing unit to perform such tasks as classification and recognition. However, the implementation of synaptic devices (i.e., the essential building blocks for emulating the functions of biological synapses) remains challenging due to their uncontrollable weight update protocol and corresponding uncertain effects on the operation of the system, which can lead to a bottleneck in the continuous design and optimization. Here, we demonstrate a synaptic transistor based on highly purified, preseparated 99% semiconducting carbon nanotubes, which can provide adjustable weight update linearity and variation margin. The pattern recognition efficacy is validated using a device-to-system level simulation framework. The enlarged margin rather than the linear weight update can enhance the fault tolerance of the recognition system, which improves the recognition accuracy.

Carbon Nanotube Synaptic Transistor Network for Pattern Recognition

Inspired by the human brain, a neuromorphic system combining complementary metal-oxide semiconductor (CMOS) and adjustable synaptic devices may offer new computing paradigms by enabling massive neural-network parallelism. In particular, synaptic devices, which are capable of emulating the functions of biological synapses, are used as the essential building blocks for an information storage and processing system. However, previous synaptic devices based on two-terminal resistive devices remain challenging because of their variability and specific physical mechanisms of resistance change, which lead to a bottleneck in the implementation of a high-density synaptic device network. Here we report that a three-terminal synaptic transistor based on carbon nanotubes can provide reliable synaptic functions that encode relative timing and regulate weight change. In addition, using system-level simulations, the developed synaptic transistor network associated with CMOS circuits can perform unsupervised learning for pattern recognition using a simplified spike-timing-dependent plasticity scheme.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric.

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Flammable carbon nanotube transistors on a nitrocellulose paper substrate for transient electronics

Transient electronics represent an emerging class of technology comprising materials that can vanish in a controlled manner in response to stimuli. In contrast to conventional electronic devices that are designed to operate over the longest possible period, transient electronics are defined by operation typically over a short and well-defined period; when no longer needed, transient electronics undergo self-deconstruction and disappear completely. In this work, we demonstrate the fabrication of thermally triggered transient electronic devices based on a paper substrate, specifically, a nitrocellulose paper. Nitrocellulose paper is frequently used in acts of magic because it consists of highly flammable components that are formed by nitrating cellulose by exposure to nitric acid. Therefore, a complete and rapid destruction of electronic devices fabricated on nitrocellulose paper is possible without producing any residue (i.e., ash). The transience rates can be modified by controlling radio frequency signal-induced voltages that are applied to a silver (Ag) resistive heater, which is stamped on the backside of the nitrocellulose paper. The Ag resistive heater was prepared by a simple, low-cost stamping fabrication, which requires no harsh chemicals or complex thermal treatments. For the electronics on the nitrocellulose paper substrate, we employed semiconducting carbon nanotube (CNT) network channels in the transistor for superior electrical and mechanical properties.

Transparent, Flexible Strain Sensor Based on a Solution-Processed Carbon Nanotube Network

The demands for transparent, flexible electronic devices are continuously increasing due to their potential applications to the human body. In particular, skin-like, transparent, flexible strain sensors have been developed to realize multifunctional human-machine interfaces. Here, we report a sandwich-like structured strain sensor with excellent optical transparency based on highly purified, solution-processed, 99% metallic CNT-polydimethylsiloxane (PDMS) composite thin films. Our CNT-PDMS composite strain sensors are mechanically compliant, physically robust, and easily fabricated. The fabricated strain sensors exhibit a high optical transparency of over 92% in the visible range with acceptable sensing performances in terms of sensitivity, hysteresis, linearity, and drift. We also found that the sensitivity and linearity of the strain sensors can be controlled by the number of CNT sprays; hence, our sensor can be applied and controlled based on the need of individual applications. Finally, we investigated the detections of human activities and emotions by mounting our transparent strain sensor on various spots of human skins.

TCAD-Based Simulation Method for the Electrolyte–Insulator–Semiconductor Field-Effect Transistor

A simulation method for the electrolyte-insulator-semiconductor field-effect transistor (EISFET)-type sensor is proposed based on a well-established commercialized semiconductor 3-D technology computer-aided design simulator. The proposed method relies on the fact that an electrolyte can be described using a modified intrinsic semiconductor material because of the similarity between the electrolyte and the intrinsic semiconductor. The electrical double layer of the electrolyte is characterized in the simulation using the Gouy-Chapman-Stern model. Using the proposed simulation method, we extract the Debye lengths depending on phosphate buffered saline solutions with various concentrations and demonstrate that it is possible to simulate the screening effect. Furthermore, we investigate the responses of the EISFET-type silicon nanowire pH sensor based on our simulation method, which shows good agreement with the reported Nernst limit value.

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor.

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.

Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory

A fast charge loss within a few seconds, which is referred to as early retention, was observed in tube-type 2y word-line stacked 3-D NAND flash memory for the first time, and the origin of the early retention was comprehensively evaluated. Using a fast-response pulse I-V system, the early retention characteristics from microseconds to seconds were thoroughly investigated, and the correlations with various program and erase levels were examined using solid and checkerboard patterns. Our findings indicate that the early retention mainly originates from the lateral charge loss through the shared charge trap layers and suggest that the program and erase levels should be balanced and optimized to reduce the early retention.

Accurate extraction of mobility in carbon nanotube network transistors using C-V and I-V measurements

The mobility of single-walled carbon nanotube (SWNT) network thin-film transistors (TFTs) is an essential parameter. Previous extraction methods for mobility encountered problems in extracting accurate intrinsic mobility due to the uncertainty of the SWNT density in the network channel and the existence of contact resistance at the source/drain electrodes. As a result, efficient and accurate extraction of the mobility in SWNT TFTs is challenging using previous methods. We propose a direct method of extracting accurate intrinsic mobility in SWNT TFTs by employing capacitance-voltage and current-voltage measurements. Consequently, we simply obtain accurate intrinsic mobility within the ink-jet printed SWNT TFTs without any complicated calculations.