J. Garvey

Multifractal analysis of minimum bias events in\(\sqrt s \) = 630 GeV\(\bar p\)p collisions

A search for multifractal structures, in analogy with multifractal theories, is performed on UA1 minimum bias events. A downward concave multifractal spectral function,f(α) (where α is the Lipschitz-Hölder exponent), indicates that there are self-similar cascading processes, governing the evolution from the quark to the hadron level, in the final states of hadronic interactions.f(α) is an accurate measure of the bin to bin fluctuations of any observable. It is shown that the most sensitive comparison between data and the Monte Carlo models, GENCL and PYTHIA 4.8 can be made usingf(α). It is found that these models do not fully reproduce the behaviour of the data.

One Size Fits All : Multiple Uses of Common Modules in the ATLAS Level-1 Calorimeter Trigger

The architecture of the ATLAS Level-1 Calorimeter Trigger has been improved and simplified by using a common module to perform different functions that originally required three separate modules. The key is the use of FPGAs with multiple configurations, and the adoption by different subsystems of a common high-density custom crate backplane that takes care to make data paths equal widths and includes minimal VMEbus. One module design can now be configured to count electron/photon and tau/hadron clusters, or count jets, or form missing and total transverse-energy sums and compare them to thresholds. In addition, operations are carried out at both crate and system levels by the same module design.

Study of LVDS serial links for the ATLAS level-1 calorimeter trigger

This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 algorithmic processors from the Preprocessor crates. National Semiconductor’s Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit-error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10 13 per link can be achieved through compact cable connector assemblies over distances up to 20 m.

Prototype cluster processor module for the ATLAS level-1 calorimeter trigger

The Level-1 Calorimeter Trigger consists of a Preprocessor, a Cluster Processor (CP), and a Jet/Energy -sum Processor (JEP). The CP and JEP receive digitised triggertower data from the Preprocessor and produce trigger multiplicity and region-of-interest (RoI) information. The CP Modules (CPM) are designed to find isolated electron/photon and hadron/tau clusters in overlapping windows of trigger towers. Each pipelined CPM processes a total of 280 trigger towers of 8-bit length at a clock speed of 40 MHz. This huge I/O rate is achieved by serialising and multiplexing the input data. Large FPGA devices have been used to retrieve data and perform the cluster-finding algorithm. A full-specification prototype module has been built and tested, and first results will be presented.

The Final Multi-Chip Module of the ATLAS Level-1 Calorimeter Trigger Pre-processor

The final Pre-Precessor Multi-Chip Module (PPrMCM) of the ATLAS Level-1 Calorimeter Trigger is presented. It consists of a four-layer substrate with plasma-etched vias carrying nine dies from different manufacturers. The task of the system is to receive and digitize analog input signals from individual trigger towers, to perform complex digital signal processing in terms of time and amplitude and to produce two independent output data streams. A real-time stream feeds the subsequent trigger processors for recognizing trigger objects, and the other provides deadtime-free readout of the Pre-Processor information for the events accepted by the entire ATLAS trigger system. The PPrMCM development has recently been finalized after including substantial experience gained with a demonstrator MCM.

Implementation Of A First-level Calorimeter Trigger For Use At The Large Hadron Collider At CERN

A prototype first-level calorimeter trigger for use at LHC is described. The trigger is designed to operate on analogue signals sampled every 15 ns, the original design period for LHC. The prototype system takes in signals from a 6x6 array of calorimeter cells. These are digitised by FADCs and are then sent to a cluster finding module which contains nine ASICs based on a 0.8 micron CMOS gate array. Each ASIC searches for isolated energy clusters within the array and also calculates the sum of the energy in all 16 cells. The energy threshold of the cluster and of the isolation window are field programmable. The performance of the trigger has been evaluated both with test systems and in real conditions connected to a liquid-argon electromagnetic calorimeter in a test beam at CERN. The latency of this pipelined trigger system is 175 ns, including digitisation and digital processing.

Fast two dimensional cluster finding in particle physics

The cluster finding module (CFM) is part of the UA1 trigger processor. The CFM detects and counts two-dimensional clusters of electromagnetic particles. This process requires 75 ns for detection of either isolated or nonisolated clusters and 75 ns to count them. This is equivalent to a peak computational rate of 11000 MIPS (million instructions per second) per module (3000 MIPS average). The required high logic density and speed are achieved by using programmable array logic devices within a pipelined system. The design has been strongly influenced by the need for in-situ computer testing. >

The new UA1 calorimeter trigger processor

The UA1 first level trigger processor (TP) is a fast digital machine with a highly parallel pipelined architecture of fast combinational and programmable transistor-transistor logic controlled by programmable microsequencers. The TP uses 100000 ICs (integrated circuits) housed in 18 crates each containing 21 FASTBUS-sized molecules. It is hardwired with a very high level of interconnection. The energy deposited in the upgraded calorimeter is digitized into 1700 bytes of input data every beam crossing (3.8 mu s). The processor selects in 1.5 mu s events for further processing (1 in 30000). The trigger has improved hadron jet rejection, achieved by requiring low-energy deposition around the electromagnetic cluster. A missing-transverse-energy trigger and a total-energy trigger have also been implemented. >

Prototype Readout Module for the ATLAS Level-1 Calorimeter Trigger Processors

The level-1 calorimeter trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy-sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor and will provide trigger multiplicity information to the Central Trigger Processor and region-of-interest (RoI) information for the level-2 trigger. It will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. This paper will outline a readout system based on FPGA technology, providing a common solution for both DAQ readout and RoI readout for the CP and the JEP. Results of building a prototype readout driver (ROD) module will be presented, together with results of tests on its integration with level-2 and DAQ modules.

The electron/photon and tau/hadron Cluster Processor for the ATLAS First-Level Trigger - a Flexible Test System

The electron/photon and tau/hadron first-level trigger system for ATLAS will receive digitised data from approximately 6400 calorimeter trigger towers, covering a pseudo-rapidity region of ± 2.5. The system will provide electron/photon and tau/hadron trigger multiplicity information to the Central Trigger Processor, and Region of Interest information for the second-level trigger. The system will also provide intermediate results to the DAQ system for monitoring and diagnostic purposes. The system consists of four different 9U-module designs and two different chip (ASIC/FPGA) designs. This paper will outline a flexible test system for evaluating various elements of the system, including data links, ASICs/FPGAs and individual modules.