J.H. Sim

An analytical back-gate bias effect model for ultrathin SOI CMOS devices

An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed. >

Back-gate bias effect on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 77 and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V/sub B/=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V/sub B/=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field. >

Modeling the effect of back gate bias on the subthreshold behavior of a SiGe-channel SOI PMOS device

Abstract This paper reports on a simulation study on the back gate bias effect on the subthreshold behavior of a SiGe-channel SOI PMOS device using a device simulator. With a SiGe channel, the SOI PMOS device shows a smaller back gate bias effect as compared to the one without it.

An analytical back gate bias dependent threshold voltage model for SiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide. >

An analytical delayed-turn-off model for buried-channel PMOS devices operating at 77 K

A closed-formed analytical PMOS delayed-turn-off model suitable for simulation of circuits with buried-channel PMOS devices operating in the delayed-turn-off region at liquid-nitrogen temperature is presented. As verified by low-temperature PISCES results, the closed-form analytical PMOS delayed-turn-off model provides a much better accuracy for simulation of circuits operating at 77 K. >

The delayed-turn-on behavior in the accumulation-type SOI PMOS device operating at 77 K

Abstract This paper reports a unique delayed-turn-on behavior in an accumulation-type SOI PMOS device operating at 77 K based on the low-temperature PISCES simulation [J.B. Kuo and Y.W. Chen, IEEE Trans. Electron. Devices ED-39 , 348 (1992)]. As compared to the 300 K case, in the delayed-turn-on region, the accumulation-type SOI PMOS device at 77 K may not provide a larger transconductance as a result of the carrier freezeout effects in the thin film.

An analytical delayed-turn-on model for accumulation-type ultra-thin SOI PMOS devices operating at 77 K

Abstract This paper presents a closed-form analytical delayed-turn-on model for accumulation-type ultra-thin SOI PMOS devices operating in the “delayed-turn-on” regime at liquid nitrogen temperature. As verified by the low-temperature PISCES results [Kuo et al. , IEEE Trans. Electron Devices 39 , 348–355 (1992)], the closed-form analytical delayed-turn-on model provides a good explanation of the delayed-turn-on behavior.

A fully analytical back-gate bias model for n-channel silicon MESFETs with back channel implant

Abstract In this paper, a fully analytical back-gate bias effect model for n-channel silicon MESFET devices is presented. As verified by the PISCES results, the analytical n-channel silicon MESFET back-gate bias effect model provides a good accuracy in the internal potential distribution and the threshold voltage as the back gate bias is changed.

An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices

This paper reports an analytical threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide.<<ETX>>

A fully Analytical Back-Gate Bias Effect Model for n-Channel Silicon Mesefet Devices with Back Channel Implant

In this paper, a fully analytical back-gate bias effect model for n-channel silicon AIESFET devices is presented. As verified by the PISCES results, the analytical n-channel silicon MESFET back-gate bias effect model provides a good accuracy in the internal potential distribution and the threshold voltage as the back gate bias is changed.