J. Huisken

CoMPSoC: A template for composable and predictable multi-processor system on chips

A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time, creating different use-cases. Resources, such as interconnects and memories, are shared between different applications, both within and between use-cases, to reduce silicon cost and power consumption. The functional and temporal behaviour of the applications is verified by simulation and formal methods. Traditionally, designers resort to monolithic verification of the system as whole, since the applications interfere in shared resources, and thus affect each others behaviour. Due to interference between applications, the integration and verification complexity grows exponentially in the number of applications, and the task to verify correct behaviour of concurrent applications is on the system designer rather than the application designers. In this work, we propose a Composable and Predictable Multi-Processor System on Chip (CoMPSoC) platform template. This scalable hardware and software template removes all interference between applications through resource reservations. We demonstrate how this enables a divide-and-conquer design strategy, where all applications, potentially using different programming models and communication paradigms, are developed and verified independently of one another. Performance is analyzed per application, using state-of-the-art dataflow techniques or simulation, depending on the requirements of the application. These results still apply when the applications are integrated onto the platform, thus separating system-level design and application design.

Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms

The state of the art of compiling digital signal processing (DSP) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of DSP applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral DSP specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs. >

The Sprite Input Language-an intermediate format for high level synthesis

Describes a simple and powerful input language (intermediate format) for high level synthesis. The language belongs to the class of signalflow graphs. The Sprite Input Language (SIL) encompasses both the applicative constructs on which classical DSP languages like Silage are based, the functional constructs from hardware description languages like ELLA, and the operational constructs from sequential languages like Pascal and C. This is obtained by means of the single token flow model and using sets instead of single values for data modelling. The language is suited for acting as an intermediate language between the various specification languages and the silicon compilation system, as well as a language backbone in the synthesis part of a silicon compiler.<<ETX>>

Power-efficient application-specific VLIW processor for turbo decoding

A method permits coprocessors to be embedded inside a programmable VLIW processor. Synchronization of the coprocessors and the VLIW processor is determined at compile-time by the VLIW scheduler. The implementation of a power-efficient turbo decoder demonstrates the effectiveness of this method.

A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcasting

Orthogonal frequency division multiplex (OFDM) modulation makes possible heterogenous broadcasting networks in which satellites and terrestrial transmitters share the same frequency. A single-chip channel demodulator and decoder IC (DABchic) for consumer receiver products is based on the new digital audio broadcasting (DAB) standard. The challenging aspects in the design are: level of integration, silicon cost, design time, and power dissipation.

Ultra Low Power ASIP Design for Wireless Sensor Nodes

This work presents a methodology for designing an ultra low power application specific instruction set processor. This paper shows the different steps to develop a digital signal processing architecture for a single channel ECG application assuming a system level power dissipation constraint of 100 muW. We follow a bottleneck driven approach based on the following steps. First coarse grained clock gating is applied. Next, the static as well as the dynamic dissipation of the digital processor is reduced and possibilities for future improvements are discussed. Finally, an optimal processor is built consuming 8.40 muW when running the reference application.

An 8MIPS CMOS digital signal processor

A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.

On the IC architecture and design of a 2 &#181;m CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011

A 2µm CMOS Digital Signal Processor (PCB5010 / PCB5011), capable of eight million instructions per second (8MIPS), and up to 6 concurrent operations in each instruction will be described [1]. This high throughput results from a highly parallel architecture (see Fig. 1) with high-speed data handling capability. It contains two 16b data buses, two primary execution units, five I/O interfaces, a data ROM, two data RAMs, and flexible addressing of on and off-chip memory using three address computation units. Benchmarks show a two to six times improvement in overall performance over its predecessors.

Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies

The growing complexity of multiprocessor systems on chip make the integration of Intellectual Property (IP) blocks into a working system a major challenge. Networks-on-Chip (NoCs) facilitate a modular design approach which addresses the hardware challenges in designing such a system. Guaranteed communication services, offered by the AEthereal NoC, address the software challenges by making the system more robust and easier to design. This paper describes two existing bus-based reference designs and compares the original interconnects with an AEthereal NoC. We show through these two case study implementations that the area cost of the NoC, which is dominated by the number of network connections, is competitive with traditional interconnects. Furthermore, we show that the latency in the NoC-based design is still acceptable for our application.

A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability

A 2-/spl mu/m CMOS VLSI digital signal processor (DSP) family, the SP50, is described that is capable of eight million instructions per second and up to six concurrent operations in each instruction. Two DSPs, the PCB5010 and PCB5011, have been developed. Both are based on a common architecture which contains two 16-bit data buses, and a 16/spl times/16/spl rarr/40-bit multiplier accumulator and 16-bit ALU, both with multiprecision support in hardware. Also implemented are two static data RAMs (128/spl times/16 or 256/spl times/16), a data ROM (51/spl times/16), a 15-word three-port register file, three address computation units, and five serial and parallel I/O interfaces. The data path is controlled by an orthogonal instruction set, using 40-bit microcode words. The controller contains a five-level stack and an instruction repeat register, and can have either on-chip program memory (RAM: 32/spl times/40; ROM: 987/spl times/40) or off-chip program memory (up to 64K/spl times/40). Benchmarks show a two to sixfold improvement in overall performance over its predecessors.