Antoine Delaruelle

A high-quality digital audio filter set designed by silicon compiler CATHEDRAL-1

The semi-automatic design and custom integration of a high-quality digital audio preamplifier filter set are described. The set consists of an offset filter, ten graphic equalizer sections, and a scratch filter with a worst-case overall signal-to-noise ratio of 10 dB. The silicon compiler CATHEDRAL-1 supports the design from specifications to layout. The combination of efficient synthesis tools with optimisation at all design levels leads to a very compact silicon integration, compared with a general-purpose signal processor approach. An experimental chip is described on which the offset filter, three equalizer sections, and the scratch filter are integrated. The silicon area is 243 mm/SUP 2/ in a conservative 6-/spl mu/m NMOS technology or 8 mm/SUP 2/ when scaling down to 3-/spl mu/m technology, allowing for functional densities up to 0.2 mm/SUP 2/ pole zero, comparable with area requirements for typical switched-capacitor filters. The total filter set requires only 20 mm/SUP 2/ in a 3-/spl mu/m NMOS technology, which demonstrates the potential for low-cost digital high-fidelity signal processing.

Synthesis of synchronous communication hardware in a multiprocessor architecture

ESPA is a high level synthesis tool targeted at the design of synchronous communication hardware in a multiprocessor architecture. IO communication can also be handled. It makes use of a new memory based architectural model which allows ESPA to generate efficient solutions for audio, speech and telecom applications. This will be shown using a complex example taken from a compact disc application.

An 8MIPS CMOS digital signal processor

A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b orthogonal instruction set and supports up to six concurrent arithmetic and data-move operations in each instruction.

A 2-/spl mu/m CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank

In this paper a 2-/spl mu/m CMOS, microprogrammable Signal Processor Core (SPC) is described,intended as the number crunching unit in single-chip general purpose digital signal processors. This core contains a 16 X 16 bit paralleI multiplier, a 40-bit multiprecision accumulator, a 40--32-bit extractor, an overflow detection unit, a format adjuster, and a three-port register file for local storage of 15 operands. Its 100-ns throughput rate makes it highly suitable for signal processing systems with sample rates up to 50 kHz (speech, telecom, and HiFi audio). The architecture of this unit is discussed in detail.The design approach, using full-custom cells, bit-sliced functional blocks, and a complete bottom-up logical verification of mask data, is also discribed. The Signal Processor Core contains 19 200 transistors on a 15.5-mm/sup 2/ area. This compares with a packing density of 1200 transistors/mm/sup 2/.

On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011

A 2µm CMOS Digital Signal Processor (PCB5010 / PCB5011), capable of eight million instructions per second (8MIPS), and up to 6 concurrent operations in each instruction will be described [1]. This high throughput results from a highly parallel architecture (see Fig. 1) with high-speed data handling capability. It contains two 16b data buses, two primary execution units, five I/O interfaces, a data ROM, two data RAMs, and flexible addressing of on and off-chip memory using three address computation units. Benchmarks show a two to six times improvement in overall performance over its predecessors.

A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability

A 2-/spl mu/m CMOS VLSI digital signal processor (DSP) family, the SP50, is described that is capable of eight million instructions per second and up to six concurrent operations in each instruction. Two DSPs, the PCB5010 and PCB5011, have been developed. Both are based on a common architecture which contains two 16-bit data buses, and a 16/spl times/16/spl rarr/40-bit multiplier accumulator and 16-bit ALU, both with multiprecision support in hardware. Also implemented are two static data RAMs (128/spl times/16 or 256/spl times/16), a data ROM (51/spl times/16), a 15-word three-port register file, three address computation units, and five serial and parallel I/O interfaces. The data path is controlled by an orthogonal instruction set, using 40-bit microcode words. The controller contains a five-level stack and an instruction repeat register, and can have either on-chip program memory (RAM: 32/spl times/40; ROM: 987/spl times/40) or off-chip program memory (up to 64K/spl times/40). Benchmarks show a two to sixfold improvement in overall performance over its predecessors.