J.J. Liou

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements.

Eliminating parasitic resistances in parameter extraction of semiconductor device models

A network theorem based on potential functions is used for the purpose of cancelling the detrimental effect that the presence of parasitic linear elements has on procedures used for extracting the intrinsic-model parameters of semiconductor devices. The method is based on the use of an auxiliary function: the difference between the content and the co-content functions of the device. The theorem states that, for any arbitrarily connected network of linear and nonlinear branch elements, the summation of the difference functions of each of the branches is zero, and that this difference function is zero at any branch represented by a linear I-V characteristic. In establishing this theorem we also show that: (a) the summation of the contents, over all the branches, is zero; and (b) the summation of the co-contents, over all the branches, is zero. To illustrate the procedure the intrinsic model parameters of a real p-n junction are extracted using this idea.

New approach for defining the threshold voltage of MOSFETs

The threshold voltage of MOSFETs has traditionally been defined as the gate voltage required to cause the surface potential to be equal to twice the Fermi potential in the bulk of semiconductor. Such a definition, although widely used for modeling long-channel MOSFETs, becomes increasingly questionable for modern devices with diminishing channel lengths. In this paper a new approach is proposed which defines the threshold voltage based on the intersection of the two asymptotes of the surface potential for the depletion and strong inversion regions. The approach is tested in a simulation environment for MOS devices having different channel lengths, oxide thicknesses, and substrate doping concentrations.

Introductory invited paper On the extraction of the source and drain series resistances of MOSFETs

This article reviews and scrutinizes various proposed methods to extract the individual values of drain and source resistances (RD and RS) of MOSFETs, which are important device parameters for modeling and circuit simulation. In general, these methods contain three basic steps: (1) the extraction of the total drain and source resistance

An improved model for substrate current of submicron MOSFETs

Abstract Substrate current is a good indicator for the hot-carrier and electrostatic discharge related reliability of MOSFET. This paper develops an improved and analytic model for such a current based on the length of and maximum electric field in the high-field region near the drain junction. The present model is compared against several existing substrate current models reported in the literature, and results from device simulation and measurements are also included in support of the model development.

Modeling and measurement approaches for electrostatic discharge in semiconductor devices and ICs: an overview

Electrostatic charges can be generated everywhere. When they are discharged through semiconductor devices and integrated circuits, an event called an electrostatic discharge (ESD), failure of electronics systems using these devices and ICs can occur. This paper first gives an overview of the ESD sources and models. Then the emphasis is placed on the modeling and measurements of the most commonly used of these models called the human body model (HBM). Various HBM protection circuits are examined to look at ways of preventing ICs from being damaged should ESD events occur. The issue of HBM measurements is also addressed so that the rapid transient associated with this ESD model can be accurately measured and characterized.

A procedure to extract mobility degradation, series resistance and threshold voltage of SOI MOSFETs in the saturation region

Parasitic series resistance and mobility degradation are two important parameters for modeling and circuit simulation of MOSFETs. We present a new method to extract these two parameters from the current-voltage characteristics of SOI MOSFETs biased in the saturation region. This method is based on an integration function which reduces errors associated with the extraction procedure. Measured data and simulation results of SOI MOSFETs are used to test and verify the present method.

An electrostatic discharge failure mechanism in semiconductor devices, with applications to electrostatic discharge measurements using transmission line pulsing technique

Abstract Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip damage each year. This paper focuses on an ESD event resulting from the charge being transferred from a human body to an integrated circuit (called the human body model, HBM). In particular, the study provides simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the HBM stress. Based on this mechanism, the correct pulse needed to measure the HBM ESD characteristics using the transmission line pulsing technique is also determined and recommended.

Total ionizing dose sensitivity of function blocks in FRAM

Abstract The total ionizing dose (TID) sensitivity of the function blocks, including the memory array, sense amplifier, row decoder, column decoder and I/O port, of the ferroelectric random access memory (FRAM) are investigated. An X-ray microbeam is used for the selective irradiation and detailed detection. The ferroelectric memory array is proved to have higher resistance to TID than the peripheral control circuitry, whereas the sense amplifier is the most sensitive parts in the FRAM circuitry. The failure phenomenon is studied when each function block is irradiated, and the failure mechanism is discussed based on each block’s technological and circuital characteristics. In addition, the Co-60 γ ray irradiation test is also performed to offer a comparison of the spot and global irradiation.

Parameter extraction using lateral and vertical optimization

We revisited the direct lateral optimization method, which is based on the approach of minimizing the error on the lateral axis. We compare the efficiency and robustness of the widely used vertical optimization and the present lateral optimization methods.