Gregg D. Croft

ESD protection using a variable voltage supply clamp

Abstract This paper discusses the advantages and limitations of using supply clamping networks for electrostatic discharge (ESD) protection of integrated circuits (ICs). In addition, this paper presents an innovative supply clamp circuit that attempts to address some of the limitations of the more traditional supply clamping methods. This new circuit varies its clamp voltage depending upon whether or not the IC is mounted in a printed circuit board. If the IC is not mounted the clamp voltage is set at a very low value for maximum ESD protection. However, once the IC is mounted, the clamp voltage is increased to a value greater than the supply voltage to avoid interfering in the normal operation of the IC. Voltage versus current ( V / I ) characteristics of this supply clamp circuit are compared for the mounted versus unmounted cases. In addition, human body model (HBM) ESD threshold levels are compared for protected versus unprotected ICs. HBM ESD thresholds were seen to increase from as low as 500 V to greater than 4000 V due to the addition of a protection network incorporating this clamp circuit.

Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a comprehensive computer-aided design tool for ESD applications. Specifically, the authors develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. The key components relevant to ESD in the MOS model are studied and the implementation procedure is discussed. Experimental data measured from the human body model tester are included in support of the model.

Modeling and measurement approaches for electrostatic discharge in semiconductor devices and ICs: an overview

Electrostatic charges can be generated everywhere. When they are discharged through semiconductor devices and integrated circuits, an event called an electrostatic discharge (ESD), failure of electronics systems using these devices and ICs can occur. This paper first gives an overview of the ESD sources and models. Then the emphasis is placed on the modeling and measurements of the most commonly used of these models called the human body model (HBM). Various HBM protection circuits are examined to look at ways of preventing ICs from being damaged should ESD events occur. The issue of HBM measurements is also addressed so that the rapid transient associated with this ESD model can be accurately measured and characterized.

Die-counting algorithm for yield modeling and die-per-wafer optimization

This paper presents a computer algorithm for accurately counting the total number of possible yielding die sites on a wafer. This algorithm takes into account such variables as the X and Y die dimensions, the size and orientation of the wafer flat(s), the size of the non-yielding periphery zone, and the position of the die array relative to the center of the wafer. This algorithm can be used in conjunction with a variety of different yield models to increase each models ability to predict accurate die per wafer yields. In addition to applications in yield modeling, this die counting algorithm may also be used as a tool for increasing yields or decreasing circuit layout cycle time. Several examples of these alternate applications are presented.

On chip ESD protection using SCR pairs

Abstract A theoretical ideal ESD protection circuit is discussed, and a novel protection network modeled after the ideal circuit is presented. This novel protection network provides discharge paths between all possible pin combinations on an integrated circuit (IC) by employing complementary pairs of SCRs connecting all I/O pin and intermediate supply pins to the most negative and the most positive supply rails. The configuration of these SCR pairs allows the network to maximize its ability to protect by adjusting its d v /d t [2] threshold as the integrated circuit is powered up and powered down. During the powered down state the d v /d t threshold of the protection network is set very low to provide maximum protection for the IC. However, once the IC is powered up, the d v /d t threshold of the protection network is increased significantly to prevent it from being triggered by the normal voltage transitions of the input and output signals. The configuration of these SCR pairs also serves to minimize the parasitic capacitance and leakage currents that this protection network adds to all of the I/O pins. This characteristics allows this network to be used with certain classes of integrated circuits, such as op amps, that were previously very difficult to protect without greatly degrading thei operating characteristics. ESD thresholds and electrical performance for devices both with and without this network are compared. Human body model ESD thresholds were seen to improve from below 500 volts to as high as 6000 volts with only slight degradation seen in device performance.

Transient supply clamp with a variable RC time constant

Abstract This paper summarizes several basic supply clamping techniques and presents an innovative transient clamp circuit that makes use of some properties of a variable voltage clamp. This circuit varies its RC time constant dependent upon whether or not the integrated circuit (IC) is mounted on a printed circuit (PC) board. If the IC is mounted the time constant of the transient clamp is set very short so it will not interfere in the normal operation of the device. However, if the IC is free standing the RC time constant is set much longer to insure the clamp will stay on long enough to discharge the entire ESD pulse should the need arise. This clamp circuit was used as a component in the electrostatic discharge (ESD) protection network for an analog intermediate frequency (IF) Limiter IC. Human Body Model (HBM) ESD levels increased from less than 300 V to greater than 2000 V due to the addition of this protection network.

Modeling on-chip interconnect lines in RF circuits using "biointelligence"

Fully automated simulators have been quite successful at modeling on-chip interconnect in digital circuits. RF circuits, however, lend an extra set of challenges that make full automation difficult and often impractical. The need for accurate coupled inductance and substrate modeling are two of the difficulties. Furthermore, a more detailed knowledge of the circuit (such as which lines compose a differential pair) is often required. Rather than extraction from a nearly finished layout, the problem definition, in this work, starts and ends with the user. Lower level functionality is then provided to minimize the tedium, to make experimentation of the layout easier, and to help the user best understand the effect of each line and each parasitic on the circuit. As important, an equivalent compact model is provided without excessive generation time and without severely increasing the circuit simulation time.