Joseph C. Bernier

A method for determining a transmission line pulse shape that produces equivalent results to human body model testing methods

Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip damage each year. This paper focuses on an ESD event resulting from the charge being transferred from a human body to an integrated circuit (i.e. the human body model, HBM). In particular, the study provides simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the HBM stress. Based on this mechanism, the correct pulse needed to measure the HBM ESD characteristics using the transmission line pulse (TLP) technique is also determined and recommended.

An improved model for substrate current of submicron MOSFETs

Abstract Substrate current is a good indicator for the hot-carrier and electrostatic discharge related reliability of MOSFET. This paper develops an improved and analytic model for such a current based on the length of and maximum electric field in the high-field region near the drain junction. The present model is compared against several existing substrate current models reported in the literature, and results from device simulation and measurements are also included in support of the model development.

A physics-based model for the substrate resistance of MOSFETs

A compact and accurate model for the substrate resistance is essential and critical for the characterization of MOSFET operation, particularly for the case of relatively large drain current and sizeable substrate current. This paper develops such a model taking into account the effects of device geometry, impact ionization, and conductivity modulation. Comparison of the present and existing models is given, and results obtained from device simulation are included in support of the model. 2002 Published by Elsevier Science Ltd.

An electrostatic discharge failure mechanism in semiconductor devices, with applications to electrostatic discharge measurements using transmission line pulsing technique

Abstract Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip damage each year. This paper focuses on an ESD event resulting from the charge being transferred from a human body to an integrated circuit (called the human body model, HBM). In particular, the study provides simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the HBM stress. Based on this mechanism, the correct pulse needed to measure the HBM ESD characteristics using the transmission line pulsing technique is also determined and recommended.

An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs

Transmission line pulsing (TLP) is a useful technique to characterize electrostatic discharge (ESD) events in semiconductor devices. The pulse waveforms generated by a typical TLP set-up, however, are often distorted and oscillatory. In this paper, a new and simple experimental set-up is developed to improve the shape of the TLP waveforms and thus to increase the effectiveness of the TLP technique. Experimental results obtained from the conventional and improved set-ups are presented and compared.

Failure Analysis Techniques

Failure analysis is a necessary part of any semiconductor manufacturer’s operation. Failure analysis is the tool used for product and process improvement. Without failure analysis it is impossible to determine the cause of failure and implement corrective actions to prevent its reoccurrence. ESD related failures come from two primary sources. The first are failures produced by the ESD testers as a result of product classification. Part of a new product’s qualification process includes determining its ESD threshold and in turn, its ESD classification. Samples of parts are tested using the three ESD models detailed in Chapter 1. The parts that fail may require failure analysis to determine the weaknesses in the design or to learn how to improve the design. The other source of ESD related failure is product failure during manufacture or from the field. These failures may be caused by ESD or they could be caused by any number of failure mechanisms. The product failures where the source of the failure is not known require more methodical analysis so these other failure sources can be evaluated. This section will not attempt to provide an exhaustive review of failure analysis techniques but will focus on the techniques employed with failures originating from ESD testing. The general concepts reviewed here are applicable to any failure analysis but may not cover all of the steps and techniques available to locate failures that are not ESD related.

Physics and Models of an ESD Event

Electrostatic discharge (ESD) events occur all around us. We might not know these events by the name ‘ESD’ but nevertheless they happen. The first time many people experienced ESD was on a cold dry winter day as a child. Going out of the house we walked across the carpet not knowing that the act of walking was charging our bodies to 1000’s of volts. Unsuspectingly, we reached for the door to open it and go outside. As our hand approached the doorknob a small spark flashed between our hand and the doorknob. The spark scared us and also hurt. The doorknob was at a lower potential than our bodies. This caused the charge to pass from our body through our hand to the doorknob. Confused we asked our parents. They probably just said, “You just shocked yourself. Go on out and play” Being more careful we opened the door but this time there was no shock because we had been discharged already. Even though we were confused we went on out and played.

Chip Level Protection

Chapter 3 reviewed one form of protection — environmental protection. This focused on reducing the likelihood that an ESD event would occur and minimizing the magnitude of any discharge. The problem with only doing this form of protection is the fact that having an ESD event is inevitable. At some point in a part’s useful life it will be exposed to an ESD event. It is not sufficient to assume that the level of the ESD event will be low enough to allow it to continue to function. The designer must assume the responsibility for providing the most robust circuit that can be built within the constraints of the project. This brings us to the focus of this chapter — providing chip level protection. Chip level protection has two aspects that are key to its success. The first is directing the charge (current) through elements designed to carry it without being destroyed. The second is clamp the voltage produced by the conduction path below the voltage that causes damage. Conducting the current and clamping the voltage are the key points to providing ESD protection. The goal is to minimize the current density and electric field in a device during the ESD event [4–1].