J.L. Titus

A conceptual model of a single-event gate-rupture in power MOSFETs

Proposes a physical model of hole-collection following a heavy-ion strike to explain the development of oxide fields sufficient to cause single-event gate rupture (SEGR) in power MOSFETs. It is found that the size of the maximum field and the time at which it is attained are strongly affected by the hole mobility. Oxide fields larger than the intrinsic breakdown strength of the oxide can arise from the holes collecting at the interface and their image charge in the gate electrode. These high fields persist for times of the order of picoseconds. It is not known how long these fields must persist to initiate SEGR. >

Single-event gate rupture in vertical power MOSFETs; an original empirical expression

An empirical expression is derived that describes the susceptibility of a power double-diffused metal-oxide semiconductor (DMOS) field-effect transistor (FET) to single-event gate rupture (SEGR) induced by the interaction of mono-energetic ions with regions of the n-epi, gate oxide, and polysilicon gate. Using this expression, the failure threshold voltages for the gate and drain can be analytically determined for any particular value of energy deposition along the ions path or more commonly described as the ions linear energy transfer (LET) function. This paper delineates our research, an in-depth study of vertical power DMOS transistors, having a 50-nm gate oxide and a strong SEGR response, subjected to various mono-energetic ions, representing particular values of LET between 0 and 83 MeV cm/sup 2/ mg/sup -1/. A description of the devices characterized, the test setup and test methodology employed, the failure threshold voltages measured, and the analysis techniques used are all summarized. Finally, an empirical equation is presented that portrays the locus of SEGR in the {-V/sub GS/, V/sub DS/} plane for all values of LET. >

Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expression

This paper investigates the role that the gate oxide thickness (T/sub ox/) plays on the gate and drain failure threshold voltages required to induce the onset of single-event gate rupture (SEGR). The impact of gate oxide thickness on SEGR is experimentally determined from vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) having identical process and design parameters, except for the gate oxide thickness. Power MOSFETs from five variants were specially fabricated with nominal gate oxide thicknesses of 30, 50, 70, 100, and 150 nm. Devices from each variant were characterized to mono-energetic ion beams of Nickel, Bromine, Iodine, and Gold. Employing different bias conditions, failure thresholds for the onset of SEGR were determined for each oxide thickness. Applying these experimental test results, a previously published empirical expression is extended to include the effects of gate oxide thickness. In addition, observations of ion angle, temperature, cell geometry, channel conductivity, and curvature at high drain voltages are briefly discussed.

Effect of ion energy upon dielectric breakdown of the capacitor response in vertical power MOSFETs

The effect of ion energy upon the ion-induced dielectric breakdown response of the capacitor response in vertical power metal-oxide semiconductor field effect transistors (MOSFETs) was investigated. The single event gate rupture response was experimentally determined using mono-energetic ion beams of copper, niobium, and gold. Irradiations were conducted using an ion species tuned to different energies, producing a range of linear energy transfer (LET) values for that ion. Numerous MOSFETs were characterized to identify the onset of ion-induced dielectric breakdown. These data along with previously taken data demonstrated that the ion-induced dielectric breakdown cannot be adequately described in terms of LET, but is better described in terms of atomic number (Z). Based upon these observations, a new semi-empirical expression is presented describing the critical ion-induced breakdown response in terms of Z instead of LET. This expression is shown to be a better single event gate rupture model of the capacitor response.

SEGR and SEB in n-channel power MOSFETs

For particular bias conditions, it is shown that a device can fail due to either single-event gate rupture (SEGR) or to single-event burnout (SEB). The likelihood of triggering SEGR is shown to be dependent on the ion impact position. Hardening techniques are suggested.

Evaluation of proposed hardness assurance method for bipolar linear circuits with enhanced low dose rate sensitivity (ELDRS)

Data are presented on several low dose rate sensitive bipolar linear circuits to evaluate a proposed hardness assurance method. The circuits include primarily operational amplifiers and voltage comparators with a variety of sensitive components and failure modes. The proposed method, presented in 1997, includes an option between a low dose rate test at 10 mrd(Si)/s and room temperature and a 100/spl deg/C elevated temperature irradiation test at a moderate dose rate. The results of this evaluation demonstrate that a 10 mrd(Si)is test is able (in ail but one case) to bound the worst case response within a factor of 2. For the moderate dose rate, 100/spl deg/C test the worst case response is within a factor of 3 for 8 of 11 circuits, and for some circuits overpredicts the low dose rate response. The irradiation bias used for these tests often represents a more degrading bias condition than would be encountered in a typical space system application.

Influence of ion beam energy on SEGR failure thresholds of vertical power MOSFETs

For the first time, experimental observations and numerical simulations show that the impact energy of the test ion influences the single-event gate rupture (SEGR) failure thresholds of vertical power MOSFETs. Current testing methodology may produce false hardness assurance.

Enhanced low dose rate sensitivity (ELDRS) of linear circuits in a space environment

To investigate the ELDRS effect in a real space environment, an experiment was designed, launched, and placed in a highly elliptical orbit in November 1997. After its deployment, the electrical responses of several bipolar transistors and linear circuits have been and continue to be recorded once during every 12-hour orbit. System dosimeters are monitored to establish an average accumulated dose per orbit. With this information, the electrical parameter data are correlated with the dosimetry data to determine the total dose response of each device. This paper updates information on the ELDRS experiment through May 14, 1999. As of this date, the experiment has been in flight for a period of 18 months and has accumulated an approximate dose of 18 krd(Si). For comparison, devices, specifically linear circuits with the same date code, were irradiated using Co-60 sources, herein defined as ground-based tests. The ground-based tests are used to evaluate two hardness assurance tests, a room temperature irradiation at 10 mrd(Si)/s and an elevated temperature irradiation at 100/spl deg/C and 10 rd(Si)/s and to evaluate the ELDRS response. To that end, irradiations were performed at room temperature, approximately 22/spl deg/C, at fixed dose rates of 100, 1, and 0.01 rd(Si)/s and at elevated temperature, approximately 100/spl deg/C, at a fixed dose rate of 10 rd(Si)/s. Currently, irradiations are being performed at room temperature at a fixed dose rate of 0.001 rd(Si)/s. Comparing the ground-based data to the flight data clearly demonstrates that enhanced parametric degradation has occurred in the flight parts. The two hardness assurance screens predicted ELDRS but the design margin for the elevated temperature test may not be adequate.

SEGR response of a radiation-hardened power MOSFET technology

SEGR response curves are presented for eighteen different device types of radiation-hardened power MOSFETs. Comparisons are made to demonstrate the technologys insensitivity to die size, rated blocking voltage, channel conductivity, and temperature. From this data, SEGR cross-sectional area curves are inferred.

First observations of enhanced low dose rate sensitivity (ELDRS) in space: One part of the MPTB experiment

Bipolar devices, most notably circuits fabricated with lateral PNP transistors (LPNP) and substrate PNP transistors (SPNP), have been observed to exhibit an enhanced low dose rate sensitivity when exposed to ionizing radiation. These dose rate sensitive bipolar devices exhibited enhanced degradation of base current in transistors and of input bias current, offset current, and/or offset voltage in linear circuits at dose rates less than 0.1 rd(Si)/s compared to devices irradiated at dose rates greater than 1 rd(Si)/s. The total dose responses of several bipolar transistors and linear circuits in a space environment are demonstrated to exhibit enhanced degradation comparable, in magnitude, to ground-based data irradiated at a dose rate of 10 mrd(Si)/s indicating that enhanced low dose rate sensitivities (ELDRS) do indeed exist in space.