M. Allenspach

A conceptual model of a single-event gate-rupture in power MOSFETs

Proposes a physical model of hole-collection following a heavy-ion strike to explain the development of oxide fields sufficient to cause single-event gate rupture (SEGR) in power MOSFETs. It is found that the size of the maximum field and the time at which it is attained are strongly affected by the hole mobility. Oxide fields larger than the intrinsic breakdown strength of the oxide can arise from the holes collecting at the interface and their image charge in the gate electrode. These high fields persist for times of the order of picoseconds. It is not known how long these fields must persist to initiate SEGR. >

Evaluation of SEGR threshold in power MOSFETs

Bias values, determined experimentally to result in single-event gate rupture (SEGR) in power metal oxide semiconductor field effect transistors (MOSFETs), are used in 2-D device simulations, incorporating the experimental geometry. The simulations indicate that very short time oxide field transients occur for ion strikes when V/sub DS//spl ne/OV. These transients can affect SEGR through hole trapping and redistribution in the oxide. >

SEGR and SEB in n-channel power MOSFETs

For particular bias conditions, it is shown that a device can fail due to either single-event gate rupture (SEGR) or to single-event burnout (SEB). The likelihood of triggering SEGR is shown to be dependent on the ion impact position. Hardening techniques are suggested.

Single-event gate-rupture in power MOSFETs: prediction of breakdown biases and evaluation of oxide thickness dependence

Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drain biases is presented. The method requires as input the critical gate bias vs. LET for V/sub DS/=0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.

Temperature and angular dependence of substrate response in SEGR [power MOSFET]

This work examines the role of the substrate response in determining the temperature and angular dependence of Single-Event Gate Rupture (SEGR) in a power MOSFET. Experimental data indicate that the likelihood of SEGR increases when the temperature of the device is increased or when the incident angle is made closer to normal. In this work, simulations are used to explore this influence of high temperature on SEGR and to support physical explanations for this effect. The reduced hole mobility at high temperature causes the hole concentration at the oxide-silicon interface to be greater, increasing the transient oxide field near the strike position. In addition, numerical calculations show that the transient oxide field decreases as the ions angle of incidence is changed from normal. This decreased field suggests a lowered likelihood for SEGR, in agreement with the experimental trend. >

Influence of ion beam energy on SEGR failure thresholds of vertical power MOSFETs

For the first time, experimental observations and numerical simulations show that the impact energy of the test ion influences the single-event gate rupture (SEGR) failure thresholds of vertical power MOSFETs. Current testing methodology may produce false hardness assurance.

Measurement of a cross-section for single-event gate rupture in power MOSFETs

The heavy-ion fluence required to induce Single-Event Gate Rupture (SEGR) in power MOSFETs is measured as a function of the drain bias, V/sub DS/, and as a function of the gate bias, V/sub GS/. These experiments reveal the abrupt nature of the SEGR-voltage threshold. In addition, the concepts of cross-section, threshold, and saturation in the SEGR phenomenon are introduced. This experimental technique provides a convenient method to quantify heavy-ion effects in power MOSFETs.

A physical interpretation for the single-event-gate-rupture cross-section of n-channel power MOSFETs

The single-event-gate-rupture cross-section is measured as a function of drain-source and gate-source bias for some n-channel power MOSFETs. The experimental techniques are explained, and the results are interpreted with the help of two-dimensional computer modeling.

Experimental evidence of the temperature and angular dependence in SEGR [power MOSFET]

The temperature and angular dependence of Single-Event Gate Rupture (SEGR) experiments, conducted on power DMOS transistors, show that a normal incident angle favors SEGR and elevated temperature is insignificant. Both the oxide and substrate response play a major role in determining the SEGR sensitivity.

SEGR: a unique failure mode for power mosfets in spacecraft

Power MOSFETs are vulnerable to catastrophic single-event phenomena ena when exposed to the radiation environment of space. In particular, single-event-gate-rupture (SEGR) is a failure mechanism unique to DMOS power transistors caused by the passage of a heavy ion through the neck region of the device and the subsequent transient electric field across the gate oxide. This paper will describe the failure mode, present supporting experimental data, and demonstrate an effective simulation tool for predicting gate rupture.