J. Lacord

Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures

In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations.

Simple and Efficient MASTAR Threshold Voltage and Subthreshold Slope Models for Low-Doped Double-Gate MOSFET

In this brief, we propose simple and analytical models for threshold voltage and subthreshold slope including short-channel and quantum effects for fully depleted or undoped double-gate MOS devices.

Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices

In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, validated through 3-D TCAD simulations, accounts for gate contact, advanced process bricks, such as gate last, BAR contact, and low-

Reconfigurable field effect transistor for advanced CMOS: A comparison with FDSOI devices

k

Impact of carrier lifetime on Z 2 -FET operation

spacer, but also multilayer dielectric by introducing an equivalent permittivity. Finally, FFSOI and SNWSOI architectures are compared from this parasitic capacitance point of view.

The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies

The optimization of Reconfigurable FET (RFET) devices is carried out in planar SOI technology. The electrostatic behavior, drive current and logic inverter operation are then discussed and compared with planar 28nm FDSOI devices.

New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

A systematic study to model and characterize the band-modulation Z2-FET device is developed. Emphasis is given on the effect of carrier lifetime which is the key parameter. It provides guidelines to design Z2-FETs for sharp switching, ESD protection and 1T-DRAM applications. We provide new insights of the relation between carrier generation/recombination and electrostatic barriers.

NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

This work focuses on what drives the access resistance. Based on TCAD simulations, we evidence that the access resistance does depend on gate voltage. From this statement, after considering an access resistance compact model, we show that the access resistance voltage dependence generates an artificial short channel mobility collapse. Based on actual silicon data we establish link between μo-L and Rac-Vg. In particular this relation predicts that negative resistance could be extracted for narrow devices in agreement with experiments.

Impact of intermediate BEOL technology on standard cell performances of 3D VLSI

In this paper we deeply investigate the dependence of BTI with transistor scaling. Unlike PBTI, NBTI is strongly enhanced in narrow devices like Nanowire or Finfet. We clearly prove by means of 3D electrostatic simulations that it is due to a defect density at the Sidewall (SW) of the transistor about 2.5 times higher than the one at the Top Surface (TS).

Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond

In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confinement, this model is able to handle arbitrary NW/NS cross-section shape of stacked-planar and vertical GAA MOSFETs (circular, square, rectangular). This Nanowire Surface Potential (NSP) based model, validated both by numerical simulations and experimental data, is demonstrated to be very accurate in all operation regimes of GAA MOSFETs.