F. Boeuf

Plasma wave detection of terahertz radiation by silicon field effects transistors: Responsivity and noise equivalent power

Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120–300nm have been studied as room temperature plasma wave detectors of 0.7THz electromagnetic radiation. In agreement with the plasma wave detection theory, the response was found to depend on the gate length and the gate bias. The obtained values of responsivity (⩽200V∕W) and noise equivalent power (⩾10−10W∕Hz0.5) demonstrate the potential of Si MOSFETs as sensitive detectors of terahertz radiation.

Plasma wave detection of sub-terahertz and terahertz radiation by silicon field-effect transistors

We report on experiments on photoresponse to sub-THz (120GHz) radiation of Si field-effect transistors (FETs) with nanometer and submicron gate lengths at 300K. The observed photoresponse is in agreement with predictions of the Dyakonov–Shur plasma wave detection theory. This is experimental evidence of the plasma wave detection by silicon FETs. The plasma wave parameters deduced from the experiments allow us to predict the nonresonant and resonant detection in THz range by nanometer size silicon devices—operating at room temperature.

28nm FDSOI technology platform for high-speed low-voltage digital applications

For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

Sources responsible for local and inter-die threshold voltage (V_t) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local V_t variability and it is found that SOI thickness (T_Si) variations have a negligible impact down to T_Si=7 nm. Moreover, T_Si scaling is shown to limit both local and inter-die V_t variability induced by gate length fluctuations. The highest matching performance ever reported for 25 nm gate length MOSFETs is achieved (A_Vt=0.95 mV.mum), demonstrating the effectiveness of the undoped ultra-thin FDSOI architecture in terms of V_t variability control.

Multi-

This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

V_{T}

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Silicon photonics research can be dated back to the 1980s. However, the previous decade has witnessed an explosive growth in the field. Silicon photonics is a disruptive technology that is poised to revolutionize a number of application areas, for example, data centers, high-performance computing and sensing. The key driving force behind silicon photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost. This is a key enabling factor for bringing photonics to a range of technology areas where the costs of implementation using traditional photonic elements such as those used for the telecommunications industry would be prohibitive. Silicon does however have a number of shortcomings as a photonic material. In its basic form it is not an ideal material in which to produce light sources, optical modulators or photodetectors for example. A wealth of research effort from both academia and industry in recent years has fueled the demonstration of multiple solutions to these and other problems, and as time progresses new approaches are increasingly being conceived. It is clear that silicon photonics has a bright future. However, with a growing number of approaches available, what will the silicon photonic integrated circuit of the future look like? This roadmap on silicon photonics delves into the different technology and application areas of the field giving an insight into the state-of-the-art as well as current and future challenges faced by researchers worldwide. Contributions authored by experts from both industry and academia provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths. Advances in science and technology required to meet challenges faced by the field in each of these areas are also addressed together with predictions of where the field is destined to reach.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm) on UT2B devices at L<inf>G</inf>= 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

Roadmap on silicon photonics

In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

We report on the high-field (up to 10T) magnetoresistance measurements performed on the short (down to 75-nm gate length) n-type Si metal-oxide-semiconductor field-effect transistors. The electron magnetoresistance mobility of these nanometer devices was determined for a wide range of the electron concentration (107–1013cm−2, i.e., from a weak to a strong inversion) and gate length (10μm–75nm). In the case of long samples, the magnetoresistance mobility was compared to the effective mobility obtained by the standard parameter extraction and the split C–V techniques. The results are discussed in terms of the scattering power-law two-dimensional transport analysis. The data clearly indicate a significant decrease of the mobility with the gate length reduction below 100nm.