Pascal Fonteneau

Characterization of the transient behavior of gated/STI diodes and their associated BJT in the CDM time domain

A measurement setup for the characterization of very fast transient responses in the CDM time domain is described in this paper. Experimental results are demonstrated on STI and gated diodes with a guard ring in a 65 nm and 130 nm CMOS technology. The superior behavior of gated diodes during triggering is highlighted.

Innovative ESD protections for UTBB FD-SOI technology

We present an innovative set of UTBB (Ultra-Thin Body and BOX) ESD protection devices, which achieves remarkable performance in terms of leakage current and triggering control. Ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V <; Vt1 <; 2.6V) capability are demonstrated. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.

Sharp-switching Z 2 -FET device in 14 nm FDSOI technology

Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a very recent sharp switching device which achieves remarkable performance in terms of leakage current and triggering control. The device is fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator (SOI) technology, features an extremely sharp on-switch, an adjustable triggering voltage (VON), and can be considered for Electro-Static Discharge (ESD). The operation of our device relies on the modulation of electrons and holes injection barriers. In this paper, we show, for the first time, experimental data obtained on the 14 nm FDSOI (Fully Depleted SOI) node.

A sharp-switching gateless device (Z3-FET) in advanced FDSOI technology

A systematic study of a novel band modulation device (Z3-FET: Zero gate, Zero swing slope and Zero impact ionization) fabricated in most advanced Fully Depleted Silicon-On-Insulator technology is presented. Since the device has no front gate, the operation mechanism is controlled by two buried ground planes. Characteristics such as sharp switching, low leakage, and controllable triggering are measured and discussed. We explore several variants (thin and thick silicon film) and show promising results in terms of high current and switching performance.

Thickness characterization by capacitance derivative in FDSOI p-i-n gated diodes

The SOI structural characterization is addressed in this paper by using split capacitance measurements on p-i-n gated diodes. The p+ and n+ contacts supply promptly electrons and holes in the body, preventing the diode from the parasitic transient effects that undermine the capacitance measurements in SOI MOSFETs. A novel method to determine the silicon film thickness, based on the capacitance derivative, is presented and validated by experiments and TCAD simulations.

Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory

We demonstrate experimentally a capacitorless IT-DRAM fabricated with 28 nm FDSOI. The Z2-FET memory cell features a large current sense margin and long retention time at T = 25°C and 85°C. Systematic measurements show that Z2-FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory.

Novel back-biased UTBB lateral SCR for FDSOI ESD protections

For the first time, a Lateral SCR (Silicon Controlled Rectifier) with Ultra-Thin Body and Buried Oxide (UTBB) is experimentally demonstrated. This device is dedicated to Electro-Static Discharge (ESD) protection and has been designed and fabricated with 28 nm Fully Depleted SOI technology. A new control technique is proposed: the use of back-gate biasing. Characteristics such as low leakage, controllable triggering (as a function of back gate voltage and ground-plane type), and device geometry are explored. We discuss several configurations (floating or locked P-base) and show promising results in terms of ESD protection performance.

Modeling a SCR-based protection structure for RF-ESD co-design simulations

Electrostatic discharge protection is a must in every integrated circuit. At microwave frequencies, the influence the protection devices have over the circuit they protect can significantly impact the functioning of the latter. A model for the SCR (silicon controlled rectifier - one of the most efficient ESD protection devices) and the ESD protection diode was developed. Its purpose is to estimate this influence at frequencies up to 65 GHz. A complex device, the DTSCR (diode triggered SCR) is used to demonstrate the consistency of the SCR and diode models.

Novel FDSOI band-modulation device: Z 2 -FET with Dual Ground Planes

A novel sharp switching Z2-FET DGP device (Zero Impact Ionization and Zero Subthreshold Slope FET with Dual Ground Planes) relying on band modulation mechanism is presented in this paper. The device is fabricated in the most advanced FDSOI (Fully Depleted SOI) technology with Ultra-Thin Body and Buried Oxide (UTBB). The Z2-FET DGP is an upgraded version of Z2-FET. It features sharp on-switch, adjustable triggering voltage (Vt1), and wide hysteresis useful for 1T-DRAM memory.

Innovative high-density ESD protection device in state of the art UTBB FDSOI technologies

For the first time, we demonstrate an innovative way to build ESD protection in FDSOI technologies. This protection is comprised of two stacked devices one on the other: a bottom bulk-thyristor and a top thin film triggering device. Low leakage current, tunable triggering voltage and high current capability are highlighted.