J.M.C. Stork

75-GHz f/sub T/ SiGe-base heterojunction bipolar transistors

The fabrication of silicon heterojunction bipolar transistors which have a record unity-current-gain cutoff frequency (f/sub T/) of 75 GHz for a collector-base bias of 1 V, an intrinsic base sheet resistance (R/sub bi/) of 17 k Omega / Square Operator , and an emitter width of 0.9 mu m is discussed. This performance level, which represents an increase by almost a factor of 2 in the speed of a Si bipolar transistor, was achieved in a poly-emitter bipolar process by using SiGe for the base material. The germanium was graded in the 45-nm base to create a drift field of approximately 20 kV/cm, resulting in an intrinsic transit time of only 1.9 ps.<<ETX>>

Heterojunction bipolar transistors using Si-Ge alloys

Advanced epitaxial growth techniques permit the use of pseudomorphic Si/sub 1-x/Ge/sub x/ alloys in silicon technology. The smaller bandgap of these alloys allows for a variety of novel band-engineered structures that promise to enhance silicon-based technology significantly. The authors discuss the growth and properties of pseudomorphic Si/sub 1-x/Ge/sub x/ structures and then focus on their applications, especially the Si/sub 1-x/Ge/sub x/-base heterojunction bipolar transistor (HBT). They show that HBTs in the Si/sub 1-x/Ge/sub x/ system allow for the decoupling of current gain and intrinsic base resistance. Such devices can be made by using a variety of techniques, including molecular-beam epitaxy and chemical vapor deposition. The authors describe the evolution of fabrication schemes for such HBTs and describe the DC and AC results obtained. They show that optimally designed HBTs coupled with advanced bipolar structures can provide performance leverage. >

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFETs. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n/sup +/ polysilicon-gate SiGe p-MOSFETs have acceptable short-channel behavior at 0.20 /spl mu/m channel lengths and are preferable to p/sup +/ polysilicon-gate p-MOSFETs for 2.5 V operation. Experimental results of n/sup +/-gate modulation-doped SiGe p-MOSFETs illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm/sup 2//V.s at 300 K and 980 cm/sup 2//V.s at 82 K are obtained. >

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n/sup +/ polysilicon gate, and p/sup +/ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm/sup 2//V-s at 300 K and 980 cm/sup 2//V-s at 82 K were achieved in functional submicrometer p-MOSFETs.<<ETX>>

Graded-SiGe-base, poly-emitter heterojunction bipolar transistors

Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors (HBTs) fabricated using a low-temperature epitaxial technique to form the SiGe graded-bandgap base layer are discussed. These devices were fabricated on patterned substrates and subjected to annealing cycles used in advanced bipolar processing. These devices, which have base widths under 75 mm, were found to have excellent junction qualities. Due to the small bandgap of SiGe, the collector current at low bias is ten times higher than that for Si-base devices that have a pinched base resistance. This collector current ratio increases to more than 40 at LN/sub 2/ temperature resulting in current gains of 1600 for the SiGe-base transistors despite base sheet resistances as low as 7.5 k Omega / Square Operator .<<ETX>>

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations

The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided. >

Optimization of SiGe HBT technology for high speed analog and mixed-signal applications

SiGe HBTs have achieved record peak f/sub T/ values values and impressive digital circuit ECL RO delays but no analog circuit results have been reported. In this work we investigate the leverage of SiGe HBTs for analog circuits by optimizing the Ge-profile for a high /spl beta/V/sub A/ product and high f/sub T/ under the constraint of breakdown voltage and effective strain of the SiGe layer. Analytical calculations of /spl beta/, V/sub A/, and f/sub T/ of SiGe-HBTs as a function of Ge profile predict the largest performance advantage over Si BJTs for the most steeply graded Ge profile. SiGe-HBT transistors are fabricated with /spl beta/V/sub A/ products of 6160 V, BV/sub CEO/ of 3.5 V and f/sub max/ of 46 GHz, and compared to Si-BJTs fabricated with the same process. Digital performance is benchmarked by an ECL ring oscillator delay of 17.2 psec. The leverage for analog technology is demonstrated by fabrication of a 1 GHz SiGe-HBT 12 bit Digital to Analog Convertor.<<ETX>>

Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors

Bipolar transistors with phosphorus-doped emitters and sub-50 nm epitaxial bases have been fabricated in a low thermal-cycle process to explore the trade-offs between cutoff frequency, breakdown voltage and Early voltage. Record peak f/sub T/s of 73 GHz for a Si BJT and 113 GHz for a SiGe HBT with respective /spl beta/V/sub A/ products of 630 and 48,400 V were obtained for intrinsic base sheet resistances of 26 and 7 k/spl Omega/spl square/.<<ETX>>

Tunneling in base-emitter junctions

Tunneling currents in reverse-biased base-emitter junctions are investigated and analyzed. Guided by a simple analytic theory, shallow n+-p junctions are designed with a variety of different concentration profiles. Measurements of the dc electrical characteristics indicate a significant Zener tunneling component in the reverse diode current. The appearance of tunneling is ascertained by the temperature dependence, which also allows a clear distinction of other current mechanisms. The sensitivity of the current to the details of the doping profile is theoretically explained in terms of the maximum electric field in the junction and verified by SIMS andC-Vprofiling techniques. TheC-Vdata are analyzed in a novel way to obtain experimental data on the maximum electric field making the conclusions valid for any arbitrary junction. The implications of the presence of high electric fields in shallow junctions are discussed with respect to scaling bipolar transistors.