J.M. Chin

Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview

Abstract Failure analysis plays a major role in all areas of the semiconductor company especially during product development cycle, 1st silicon stage, or in wafer processes and fabrication as well as assembly and package development. Different companies have different FA flows but all FA steps will need to start with fault isolation. Fault isolation is the step to narrow down the focus area of a failing component or product to a manageable area that will allow us to (a) improve success of finding the defect that is causing the failure and, (b) significant speed up turn-around time for analysis. This paper provides an overview of all the available failure analysis on fault isolation methodologies and tools, for device/product level and expanding to package/assembly and PFA level isolation. The aim of the paper is to provide sufficient depth to each topic including some case studies to emphasize the key points related to each methodology. The tutorial will also cover some future directions/roadmaps.

Advanced scanning acoustic technique application in flip-chip devices

Micron-size embedded defects are challenging to detect using the traditional acoustic scanning microscope. This paper presents the latest acoustic techniques using Virtual Rescanning Mode™ (VRM) from Sonoscan® to successfully capture the defects localized at inter-layer dielectrics (ILD). Defects between copper trace and solder mask are more clearly seen when the magnitude of acoustic waveform changes from time domain to frequency domain.

Combining High Resolution Pulsed TIVA and nanoprobing techniques to identify drive strength issues in mixed signal circuits

This paper uses an interesting case study to highlight High Resolution Pulsed TIVA with Solid Immersion Lens (SIL) as a technique to isolate a temperature sensitive failure in a mixed signal circuitry followed by circuit analysis and Nanoprobing to confirm a drive strength issue caused by a process change.

Conductive Atomic Force Microscopy failure analysis for SOI devices

A FIB shorting technique to create a conducting path across the buried oxide to connect active silicon to silicon substrate is demonstrated to allow conductive atomic force microscopy (CAFM) failure analysis on SOI devices. CAFM is carried out at via and contact levels to provide current images that helped to localize the faulty node and also determine current-voltage characteristics at an area of interest.

Backside deprocessing technique & its novel fault isolation application

As process technologies are employed below 100nm, microprocessor fault isolation has become even more challenging. In this paper, we present a backside deprocessing methodology which extends fault isolation capability for silicon-on-insulator (SOI) based product. Die level failure analysis case studies using this novel methodology are demonstrated which greatly increase the fail site isolation/defect detection sensitivity with minimum failure analysis turn around time.

Recent advances in fault isolation for semiconductor industry

In semiconductor companies, failure analysis (FA) activities play a major role in all many areas. FA is deeply involved in new process technology development, 1st Silicon bring-up, wafer sort and backend yield improvement, product qualification and customer return analysis. RegardLeSS Of area that FA SUPPOrtS, there IS aLWaYS a need fOr faULt ISOLatIOn PrIOr tO the PhYSICaL Or deStrUCtIVe faILUre anaLYSIS. FaULt ISOLatIOn IS the SteP Where We narrOW dOWn the area Of a faILIng Part Or PrOdUCt tO a manageabLe area. ThIS aLLOWS FA engIneer tO ImPrOVe the SUCCeSS Of PhYSICaLLY fIndIng rOOt CaUSe Of the faILUre and SPeedS UP the TUrn-arOUnd tIme fOr the anaLYSIS. ThIS InVIted taLK WILL COVer reCent adVanCeS In faULt ISOLatIOn teChnIqUeS and tOOLS In deVICe/SILICOn and PaCKagIng. CaSe StUdIeS fOr thOSe teChnIqUeS WILL be COVered tO PrOVIde greater UnderStandIng fOr the teChnIqUeS tO the aUdIenCe.

Surface roughness metrology study on flip-chip substrate

Precise measurement in the nanometer range is a challenge. This paper presents the metrology to measure the surface roughness on a flip-chip substrate using AFM and optical profiler. The effects of probe geometry, parameters, and repeatability on AFM measurements are investigated. Correlation results between AFM and optical profiler are studied.

High-temperature Conductive-AFM technique for resolution of soft failures

This paper demonstrates the Veeco heating stage for high temperature Conductive-AFM analysis which is very useful for revealing leaky contacts associated with soft failures. CAFM at 80°C is performed on SOI transistors to isolate leaky polysilicon gate contacts. Nanoprobing at high temperature is performed and it shows strong correlation with the high temperature CAFM data. High temperature CAFM helped to isolate higher gate oxide leakage current in the failing transistor in SRAM memory cell.

Root cause identification of subtle filament shorts in microprocessors using nano-probing

It has been a challenge for failure analysts to isolate non-visible defects due to the limitations of failure analysis (FA) tools and techniques. Sub-nano defects are often difficult to detect, particularly in highly complex integrated circuit devices. This paper emphasizes the growing importance of nano-probing and its capability to detect subtle defects like nano-sized stringer shorts, which previously went undetected. Successful case studies involving the use of nano-probing techniques to help isolate subtle defects (i.e., those that cause device failure) will be discussed.

Device-level fault isolation of advanced flip-chip devices using scanning SQUID microscopy

This article describes how a scanning SQUID microscope (SSM) enhances the capability of device-level fault isolation on advanced 90 nm and 65 nm flip-chip microprocessor devices. SSM has proved to be very useful in isolating bump shorts and shorts in copper interconnects. For improved resolution and analyzing bumped dies, a front-side SSM technique is developed that has greatly increased success rates and analysis turn-around time. In this paper, we focus on die-level fault isolation on advanced microprocessor devices with numerous metal layers.