J. M. J. Lopes

Integration of

The integration of lanthanum lutetium oxide (LaLuO₃) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO₃/Si interface showed a very thin silicate/SiO₂ interlayer with a D_it level of 4.5 × 10¹¹ (eV · cm²)^-1. Fully depleted n/p-MOSFETs with LaLuO₃/TiN gate stacks indicated very good performance with steep subthreshold slopes of ~70 mV/dec and high I_on/I_off ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO₃ on SOI are similar to the mobilities in reported Hf-based high-κ devices.

\hbox{LaLuO}_{3} \ (\kappa \sim \hbox{30})

Amorphous LaScO3 thin films were grown on (100) Si by molecular beam deposition and the effects of postdeposition thermal treatments on the film properties were studied after anneals in O2 or inert Ar atmosphere at 400 or 650 °C. Rutherford backscattering spectrometry, transmission electron microscopy, x-ray diffraction, and x-ray photoelectron spectroscopy (XPS) were employed to investigate the samples. Capacitance-voltage and current-voltage measurements allowed their electrical characterization. Postdeposition annealing in O2 reduces hysteresis, flatband voltage, and also leakage current density. In contrast, films treated in Ar ambient revealed a different behavior. The observations were associated with the interface evolution as studied by XPS, which verify that an O2 atmosphere favors the formation of a SiO2-rich interface between the film and the Si substrate, while a La-Sc-silicate-like compound predominates in this region after treating the samples in Ar. Additionally, postdeposition annealing re...

as High-

Samarium scandate thin films deposited on (100) Si have been investigated structurally and electrically. Rutherford backscattering spectrometry and transmission electron microscopy results show that the films are stoichiometric, amorphous, and smooth. X-ray diffraction analysis indicates that SmScO3 starts to crystallize at 900 °C. Capacitance and leakage current measurements reveal C-V curves with negligible hysteresis, a dielectric constant around 29 for 6 nm thick films, low leakage current densities in the range of 10−7 A/cm2, an effective oxide charge density of ∼5×1011 cm−2, and an interface trap density of 4.5×1011 (eV cm2)−1.

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Terbium scandate (TbScO3) and lanthanum scan date (LaScO₃) have been investigated as gate dielectrics for metal-oxide-semiconductor field-effect transistors on both silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. X-ray photoelectron spectroscopy analysis revealed the presence of a silicate at the interface for TbScO³ on Si, whereas a silicate/SiO₂-like interface was found for the LaScO₃ on Si. A full replacement gate process was developed to fabricate high-κ/metal gate fully depleted transistors on SOI and sSOI. LaScO₃ transistors with a gate length of 2 μm show excellent characteristics with steep subthreshold slopes of 72 mV/dec, high I_on/I_off ratios, and electron mobility of 180 cm²/V · s for SOI and 375 cm²/V · s for sSOI at low field, which is superior to corresponding TbScO₃ de vices. All sSOI transistors showed 2 times higher electron mobility than SOI reference devices.

Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V∙s was extracted.

Effects of annealing on the electrical and interfacial properties of amorphous lanthanum scandate high-κ films prepared by molecular beam deposition

In this study, the authors present results on the structural, chemical, and electrical characterization of HfO2 thin layers on 300 mm Si wafers. The layers were prepared by atomic layer deposition using a liquid delivery system technology for metal organic precursors, which allows an accurate control of the Hf precursor. After optimization of the deposition process with an alkylamide precursor for Hf and ozone chemistry, the growth of the SiOx interfacial layer between the HfO2 layer and the Si substrate could be minimized using TiN as metal gate. In addition, the authors studied the effect of Al2O3 interfacial layers on the properties of metal-oxide-semiconductor capacitor resulting in a positive flat band voltage shift of up to ∼300 mV according to the layer thickness. Gate stacks with equivalent oxide thicknesses around 1.1 nm showed leakage current densities as low as 1.1×10−2 A/cm2 at VFB of 1 V. In addition, the capacitance-voltage curves for thin HfO2 layers indicated a negligible hysteresis, below...

SmScO3 thin films as an alternative gate dielectric

The chemical reactions at the higher-k LaLuO<inf>3</inf>/Ti<inf>1</inf>N<inf>X</inf>/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO<inf>3</inf> with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed to explore the thermal stability of the gate stack. Based on these results an integration of TiN/LaLuO<inf>3</inf> in a gatefirst MOSFET process on SOI is shown.

Rare-Earth Scandate/TiN Gate Stacks in SOI MOSFETs Fabricated With a Full Replacement Gate Process

In this contribution, results on the structural and electrical properties of high-κ REScO3 (RE = La, Gd, Tb, Sm) and LaLuO3 amorphous thin films are presented. The study reveals that these oxides are potential candidates for future integration in MOSFETs. High dielectric constants up to 30 were measured for amorphous thin films of these materials, as well as low leakage current and low interface trap densities. Very promising results for transistors processed on SOI and sSOI substrates are also shown.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

We demonstrate the integration of TbScO3, LaScO3, and LaLuO3 as alternative gate oxides for fully depleted silicon on insulator (SOI) and strained SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) with equivalent oxide thicknesses of 2.8, 2.4, and 1.55 nm, respectively. Silicate formation at the high-κ/Si interface was studied by x-ray photoelectron spectroscopy. Electrical investigations revealed good transistor performance with these novel gate oxides with permittivities in the range of 26–32 and TiN as a metal gate. Steep inverse subthreshold slopes of 72 mV/dec, high Ion/Ioff ratios over 108, and a low density of interface states of ≈5×1011 (eV cm2)−1 were achieved. MOSFETs on SOI substrates show good low field electron mobilities of 180, 183, and 188 cm2/V s for all investigated oxides. For devices on strained SOI the electron mobility was improved by a factor of 2. The measured mobilities are close to those of devices with HfO2 as gate dielectric, while offering better electrostatic c...

Atomic layer deposition of HfO2 and Al2O3 layers on 300 mm Si wafers for gate stack technology

Integration of lanthanum lutetium oxide (LaLuO<inf>3</inf>) with a к value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ∼72 mV/dec and I<inf>on</inf>/I<inf>off</inf> ratios up to 10⁹. Strained SOI (sSOI) channel devices show higher electron mobility of 385 cm²/Vs compared to the reference device on SOI which has a mobility of 188 cm²/Vs. P-MOSFETs fabricated on sSi/Si<inf>0.5</inf>Ge<inf>0.5</inf>/sSOI heterostructure with a gate first process showed a subthreshold swing of 92 mV/dec and an I<inf>on</inf>/I<inf>off</inf> ratio of 10⁵. The extracted hole mobilities are similar to the reference device with HfO<inf>2</inf> as gate dielectric, and are much higher than the hole mobilities in Si.