J. Manikandan

FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System

In this paper, two schemes for FPGA implementation of multi-class SVM based isolated digit recognition system are proposed, one using only logic elements and another using both soft-core processor and logic elements(LEs). One of the major contributions of this paper is the proposal for implementation of the decision function using only fixed point arithmetic without compromising the recognition accuracy. Compared to the scheme which uses floating point arithmetic, the proposed scheme reduces the number of LEs required by a factor of 3.29. The second scheme proposed results in about 25 times lower area compared to the first scheme. For the soft-core processor approach, a custom instruction is proposed for floating point arithmetic. Speaker dependent TI46 database of isolated digits is used for training and testing. Features are extracted using both Linear Predictive Coefficients (LPC) and Mel Frequency Cepstral Coefficients(MFCC) and features are compressed using Self Organized Feature Mapping (SOFM). This in turn is used by the SVM classifier to evaluate the recognition accuracy and the hardware resources utilized. Both the schemes proposed result in 100% recognition accuracy when implemented on Altera Cyclone II FPGA. The proposed schemes can also be used for speaker verification and speaker authentication applications. Since the scheme which uses soft-core processor requires lower area, it can be used for systems which require a large vocabulary size.

Study and evaluation of a multi-class SVM classifier using diminishing learning technique

Support vector machine (SVM) is one of the state-of-the-art tools for linear and non-linear pattern classification. One of the design objectives of an SVM classifier is reducing the number of support vectors without compromising the classification accuracy. For this purpose, a novel technique referred to as diminishing learning (DL) technique is proposed in this paper for a multiclass SVM classifier. In this technique, a sequential classifier is proposed wherein the classes which require stringent boundaries are tested one by one and once the tests for these classes fail, the stringency of the classifier is increasingly relaxed. An automated procedure is also proposed to obtain the optimum classification order for SVM-DL classifier in order to improve the recognition accuracy. The proposed technique is applied for SVM based isolated digit recognition system and is studied using speaker dependent and multispeaker dependent TI46 database of isolated digits. Both LPC and MFCC are used for feature extraction. The features extracted are mapped using self-organized feature maps (SOFM) for dimensionality reduction and the mapped features are used by SVM classifier to evaluate the recognition accuracy using various kernels. The performance of the system using the proposed SVM-DL classifier is compared with those using other techniques: one-against-all (OAA), half-against-half (HAH) and directed acyclic graph (DAG). SVM-DL classifier results in 1-2% increase in recognition accuracy compared to HAH classifier for some of the kernels with both LPC and MFCC feature inputs. For MFCC feature inputs, both HAH and SVM-DL classifiers have 100% recognition accuracy for some of the kernels. The total number of support vectors required is the least for HAH classifier followed by the SVM-DL classifier. The proposed diminishing learning technique is applicable for a number of pattern recognition applications.

Design of a real time automatic speech recognition system using Modified One Against All SVM classifier

Abstract In this paper, Texas Instruments TMS320C6713 DSP based real-time speech recognition system using Modified One Against All Support Vector Machine (SVM) classifier is proposed. The major contributions of this paper are: the study and evaluation of the performance of the classifier using three feature extraction techniques and proposal for minimizing the computation time for the classifier. From this study, it is found that the recognition accuracies of 93.33%, 98.67% and 96.67% are achieved for the classifier using Mel Frequency Cepstral Coefficients (MFCC) features, zerocrossing (ZC) and zerocrossing with peak amplitude (ZCPA) features respectively. To reduce the computation time required for the systems, two techniques – one using optimum threshold technique for the SVM classifier and another using linear assembly are proposed. The ZC based system requires the least computation time and the above techniques reduce the execution time by a factor of 6.56 and 5.95 respectively. For the purpose of comparison, the speech recognition system is also implemented using Altera Cyclone II FPGA with Nios II soft processor and custom instructions. Of the two approaches, the DSP approach requires 87.40% less number of clock cycles. Custom design of the recognition system on the FPGA without using the soft-core processor would have resulted in less computational complexity. The proposed classifier is also found to reduce the number of support vectors by a factor of 1.12–3.73 when applied to speaker identification and isolated letter recognition problems. The techniques proposed here can be adapted for various other SVM based pattern recognition systems.

Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP

Continuous, real-time speech recognition is required for various mobile and hands-free applications. In this paper, hardware implementation of real-time speech recognition system is proposed using two approaches and their performances are evaluated. The first approach uses Mel Filter Banks with Mel Frequency Cepstrum Coefficients (MFCC) as feature input and the second approach uses Cochlear Filter Banks with Zero-crossings (ZC) as feature input for recognition. The features extracted from input speech are fed to multi-class Support Vector Machine (SVM) classifier for recognition. The proposed recognition systems are implemented on a Texas Instruments TMS320C6713 floating point digital signal processor for recognizing isolated digits (0-9) and their performances are compared. It is observed that the program memory required for MFCC feature extraction is 44.42% higher than that required for feature extraction using Cochlear filters. Recognition accuracies of 93.33% and 98.67% are achieved for feature inputs from Mel filter banks and Cochlear filter banks respectively. It is also observed that the computational complexity of feature extraction using cochlear filters is 1.53 times of that required for MFCC feature extraction. The recognition performance is also studied for different combinations of test and training utterances. It is found that training using 15 utterances of each digit results in best recognition accuracy. The techniques proposed here can be adapted for various other hands-free consumer applications such as washing machines, hands-free cordless and many more.

Evaluation of Edge Detection Techniques towards Implementation of Automatic Target Recognition

The vision of Automatic Target Recognition (ATR) is through an integrated command identification architecture that combines non-cooperative and cooperative identification sensors and systems. The ATR implemented shall support development of situational awareness i.e., overall, general knowledge of the tactical battlefield environment, including the location of friendly, neutral, and enemy forces and plan of action for battle. The required operational capability will then be achieved by combining onboard data from multiple sensors and systems with indirectly supplied off board information. Edge Detection is one of the major image-processing requirements for achieving efficient and accurate target recognition in difficult domains. The on-board sensors used on combat aircraft are Electro-optic Targeting Sensors (EOTS), Infra-red (IR) sensors, Radar, Synthetic Aperture Radar (SAR) and Inverse SAR (ISAR) providing vast amount of images with different characteristics helpful for detecting targets. This paper concentrates on the assessment of advanced edge detection techniques on all types of sensor input images obtained for the implementation of automatic target recognition for air-to-air, air-to-sea and air-to-ground applications. This paper also describes the approach towards implementation of automatic target recognition for the entire range of sensor inputs. The proposed algorithm for automatic target recognition is for implementation on airborne systems with potential use on ground stations.

Design of a modified one-against-all SVM classifier

Support Vector Machine (SVM) is one of the state of-the-art tools for linear and nonlinear pattern classification. One of the design issues in SVM classifier is reducing the number of support vectors without compromising the classification accuracy. In this paper, a novel technique which requires only a subset of the support vectors is proposed. The subset is obtained by including only those support vectors for which Lagrange multiplier is greater than a threshold. In order to find the subset which yields the highest classification accuracy with the least number of support vectors in the subset, the recognition performance corresponding to subsets with different threshold values are to be evaluated and compared. The proposed technique is applied for SVM based isolated digit recognition system and is studied using speaker dependent as well as multispeaker dependent TI46 database of isolated digits. Two feature extraction techniques, one using LPC and another using MFCC are applied to the speech from the above database and the features are mapped using SOFM. This in turn is used by the SVM classifier to evaluate the recognition accuracy. The proposed technique is applied to One-Against-All (OAA) scheme and is denoted as Modified One-Against-All (M-OAA) approach in this paper. Based on this study, it is found that for MFCC feature input, the proposed M-OAA based SVM classifier approach results in reduction of support vectors by a factor of 1.86 to 18.3 with no compromise in recognition accuracy. For LPC feature input, the M-OAA based SVM classifier results in reduction of support vectors by a factor of 1.59 to 2.52 without any compromise in recognition accuracy for some cases and with a maximum of 1% degradation in recognition accuracy for some cases. The proposed approach is also applicable for other schemes such as Half-Against-Half (HAH) and Directed Acyclic Graphs (DAG) based SVM classifiers as well as for any other classification problem such as face recognition, fingerprint recognition, target recognition, speaker recognition and speaker verification.

FPGA implementation of reconfigurable modulation system

Communication systems are extensively used in a large number of applications such as radar, aerospace, naval/maritime communication, underwater communication, mobile communication and many more. The most important module in designing communication system includes design of modulators. Different applications demand different types of modulators. Reconfigurable computing is considered as a state-of-the-art approach for system design, wherein the same hardware can reconfigure itself to perform different functionalities and is hence employed for various applications. Design and implementation of reconfigurable modulators on Virtex-5 FPGA is proposed in this paper, wherein the type of modulation can be dynamically reconfigured on-the-fly based on the requirement at any particular instance. The type of modulators that are used for reconfiguration in this work includes Amplitude Modulation (AM), Frequency Modulation (FM), Frequency Shift Keying (FSK), Phase Shift Keying (PSK), and Amplitude Shift Keying (ASK). In this paper, different approaches of triggering employed for proposed reconfigurable modulator design is reported. Also the proposed design is implemented using single and two reconfigurable blocks and the results are reported. It is observed that 10.20 - 91.43% of hardware resources and 76.38% of power are saved on using the proposed reconfigurable modulator over the conventional non-reconfigurable modulator design.

FPGA implementation of isolated digit recognition system using modified back propagation algorithm

In this paper, the details of implementation of an isolated digit recognition system using NiosII soft-core processor are presented. Mel Frequency Cepstral Coefficients (MFCC) is used for feature extraction, multi layer perceptron (MLP) is used for classification and self organized feature map (SOFM) is employed for dimensionality reduction of features. Using TIDIGITS speech data base, various MLP architectures are studied and it is found that the recognition accuracy of 100% is obtained with the least computational complexity using single layer MLP with 10 hidden nodes. MLP is trained using both BP and modified BP algorithms and it is observed that MBP is 2.62 times faster than BP with 100% recognition accuracy. The digit recognition system is implemented on Altera CycloneII FPGA using hardware/software partitioning and the following observations are made: implementation of radix-4 FFT and remaining blocks for the calculation of MFCC using universal CORDIC processor as hardware/software partitioning is dasia10psila times faster compared to the complete software implementation on NiosII processor. The hardware accelerator for the NIOSII processor for implementation of MLP increases the recognition speed by a factor of 278. The technique proposed in this paper is also applicable for other soft-core processor such as Microblaze and Picoblaze.

Software Reconfigurable State-of-the-Art Communication Suite for Fighter Aircraft

Communication systems are considered as one of the major requirements for the current and next generation fighter aircrafts to complete a mission successfully. Efficient net-centric warfare and situational awareness can be achieved with modernized communication system and high-end sensors. The conventional communication systems available consist of individual systems for each functionality. In such cases, the failure of one system leads to failure of the functionality of that system and the mission has to be completed without that system. Hence there is an urge to develop a state-of-the-art on-flight software reconfigurable communication system to provide better redundancy, successful completion of mission and efficient utilization of systems on-board for fighter aircraft. In this paper, the functionality of all the on-board communication systems is explained and the design of a state-of-the-art software re-configurable communication suite is proposed for fighter aircrafts. The highlight of this architecture is that the hardware resources are shared between the systems and incase of failure of one system, the other system shall be reconfigured on-flight to take up the functionality of the failed system. The software architecture employs software code reusability for easy debugging and code verification. The proposed system is based on the concept of Software Defined Radio (SDR) and the functionality is extended from hand-held radio to entire communication system of the aircraft.

SAR Image Compression Using Steganography

Steganograhy is generally used to hide important information in a visible media mostly an image or video. In this paper, a novel scheme serving the dual purpose of concealing and compressing Synthetic Aperture Radar (SAR) images using steganography technique is proposed for aerospace and satellite applications. SAR images represent an important source of information for a large variety of applications around the world especially mapping the geographic area. SAR image compression is very important in reducing the cost of data storage and transmission in relatively slow channels. The problem is that while the volume of data collected is increasing rapidly, the ability to transmit it to ground or to store it is not increasing as fast. Also, while storage densities on archiving media are improving with technology developments, the ability to generate new data is increasing even faster. Thus there is a strong interest in developing data encoding and decoding algorithms that can obtain higher compression ratios and faster transmission of data while keeping image quality to an acceptable level. The imaging radar also called as synthetic aperture radar (SAR), moving along with the path of flight is used to build radar images with the help of backs catters. The radar images built are displayed on the cockpit display and also stored in on-board storage disks. The proposed scheme conceals the confidential SAR images built during the surveillance flight and also enables satisfactory compression of both visible and concealed SAR images. Further compression is achieved by using Lempel-Ziv-Welch (LZW) algorithm. Experimental results show that the stegano-image and the reconstructed images are visually indistinguishable from the original image. This scheme is very simple and can be easily adapted for various image processing applications.