J. Peder Bergman

Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce Vf Drift in SiC Bipolar Power Devices

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Degradation in SiC Bipolar Devices: Sources and Consequences of Electrically Active Dislocations in SiC

Prototype SiC bipolar diodes for 300A/4500V with 3.1V forward voltage prove the SiC power device performance. However, forward voltage degradation prevents industrial application. Electrical statistics are given, and the phenomenon is described by sequencing stacking fault expansion during current conduction. The sources for these faults are identified by electro luminescence to be dissociated dislocations, likely replicated from the substrate. The identification is benchmarked against KOH etch pit patterns and X-ray back reflection topographs. A variety of buffer layers to suppress the propagation of source defects from the substrate showed small improvements.

Optimization of SiC MESFET for High Power and High Frequency Applications

SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.

Dll PL Intensity Dependence on Dose, Implantation Temperature and Implanted Species in 4H- and 6H-SiC

In most semi-conductor processing ion implantation is a key technology. The drawback of ion implantation is that a great deal of lattice defects, such as vacancies, interstitials, anti sites and complexes, are introduced. The annealing behaviour of these defects is important for the viability of ion implantation as a commonly used method. In SiC a defect that is only seen after ion implantation and not after irradiation with neutrons or electrons is the D-II defect. The use of Si or C as implanted species have made it possible to investigate the D-II photoluminescence (PL) intensity dependence on an excess of either of the two constituents in SiC. The effect of performing a hot implant at 600degreesC compared to a room temperature implant was also looked into. The D-II PL intensity was measured after a 1500degreesC anneal. When the implantation was performed at room temperature the C implanted samples showed a significantly higher D-II luminescence than the Si implanted. This makes it tempting to assume that a surplus of C and likely C interstitials are involved in the defect formation. However, when the implantation is done at 600degreesC the difference between Si and C implanted samples almost disappears and a slightly higher D-II intensity can be seen in the Si implanted samples. This effect may be due to the mobility of C interstitials at temperatures above 500degreesC. This clearly demonstrates the effect of hot implantation that there is a major change in D-II PL intensity even after a 1500degreesC anneal.

Delay and distortion of slow light pulses by excitons in ZnO

istortion of light pulses in ZnO caused by both bound and free excitons is demonstrated by time-of-flight spectroscopy. Numerous lines of bound excitons dissect the pulse spectrum and induce slowdo ...

Optical Studies of Nonequilibrium Carrier Dynamics in Highly Excited 4H-SiC Epitaxial Layers

We applied picosecond four-wave mixing technique to investigate carrier diffusion and recombination in n-type 4H-SiC epilayers. The dependence of bipolar diffusion coefficient D on photocarrier density was measured in range from ~ 1017 to ~ 1020 cm-3. We determined a decrease of D value from 3.4 to 2.2 cm2/s with increase of the photoexcitation level in range from ~ 1017 to ~ 1019 cm-3, and found its increase up to 3.8 cm2/s at carrier density above 1020 cm-3. Auger recombination governed decrease of carrier lifetime from 11 ns at ~ 1017 cm-3 to 1.8 ns at ~ 1020 cm- 3 has also been observed.

Improved Epilayer Surface Morphology on 2˚ Off-Cut 4H-SiC Substrates

Homoepitaxial layers of 4H-SiC were grown with horizontal hot-wall CVD on 2˚ off-cut substrates, with the purpose of improving the surface morphology of the epilayers and reducing the density of surface morphological defects. In-situ etching conditions in either pure hydrogen or in a mixture of silane and hydrogen prior to the growth were compared as well as C/Si ratios in the range 0.8 to 1.0 during growth. The smoothest epilayer surface, together with lowest defect density, was achieved with growth at a C/Si ratio of 0.9 after an in-situ etching in pure hydrogen atmosphere.

Comparison of Carrier Lifetime Measurements and Mapping in 4H SiC Using Time Resolved Photoluminscence and μ-PCD

Carrier lifetime measurements and wafer mappings have been done on several different 4H SiC wafers to compare two different measurement techniques, time-resolved photoluminescence and microwave induced photoconductivity decay. The absolute values of the decay time differ with a factor of two, as expected from recombination and measurement theory. Variations within each wafer are comparable with the two techniques. Both techniques are shown to be sensitive for substrate quality and distribution of extended defects.

Depth-resolved carrier lifetime measurements in 4H-SiC epilayers monitoring carbon vacancy elimination

We address the key factors limiting charge carrier lifetime in 4H-SiC epilayers by demonstrating a viable method for eliminating carbon vacancy (VC) related Z1/2 lifetime killer sites and by introducing a novel approach in depth-resolved characterization of the carrier lifetimes across the epitaxial layer, which allows monitoring the efficacy of the proposed defect reduction scheme also exposing surface and interface recombination effects. We show that a moderate-temperature annealing conducted at 1500 °C for 6 hours under C-rich thermodynamic equilibrium conditions in effect eliminates carbon vacancies in epilayers to the levels below the detection limit (1011 cm-3) of DLTS measurements. The efficient reduction of VC-related Z1/2 sites upon thermal treatment is further proven by a significant increase of the minority carrier lifetime from 0.3µs to 1 µs, the upper limit apparently set by epilayer thickness dependent lifetime. Equally important is the extensive range of defect elimination as evidenced by consistently enhanced lifetime throughout entire 40 μm-thick epilayer, thus suggesting immediate practical implication as a lifetime control method suitable for variable thickness 4H-SiC epilayers.

Influence of n-type doping levels on carrier lifetime in 4H-SiC epitaxial layers

In this study we have grown thick 4H-SiC epitaxial layers with different n-type doping levels in the range 1E15 cm-3 to mid 1E18 cm-3, in order to investigate the influence on carrier lifetime. The epilayers were grown with identical growth conditions except the doping level on comparable substrates, in order to minimize the influence of other parameters than the n-type doping level. We have found a drastic decrease in carrier lifetime with increasing n-type doping level. Epilayers were further characterized with low temperature photoluminescence and deep level transient spectroscopy.