J. Wu

Microcontroller susceptibility variations to EFT burst during accelerated aging

Abstract With deterioration of the electromagnetic environment, microcontroller unit (MCU) electromagnetic susceptibility (EMS) to transient burst interference has become a focus of academia and enterprise. Most electromagnetic compatibility (EMC) studies of MCUs have not taken the effects of aging into account. However, component aging can degrade the physical parameters of an MCU and change its immunity to EMI. This paper proposes a time-equivalent interval accelerated aging methodology combining DC electrical and high temperature stresses. The test results show variations in susceptibility to electrical fast transients (EFT) burst revealing increasing susceptibility. The reasons for MCU immunity drifts in the aging process are discussed.

Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment

Abstract During the lifetime of integrated circuits in the space environment, they encounter radiation degradation, such as the total ionizing dose (TID) effect as well as intrinsic degradation mechanisms, such as the constant voltage stress (CVS) effect. This paper analyzes the effects of TID and CVS on the nFinFET with a high-κ (HfO2) metal gate (HKMG). Various dimensions and stress voltages on nFinFETs are characterized under room temperature. Experimental results show that both effects can cause the threshold voltage (Vth) of the transistor to shift towards positive. Compared with TID-induced degradation, the devices appear relatively robust against CVS.

Investigations on immunity of interfaces between intelligent media processor and DDR3 SDRAM memory

Abstract Due to the complexity of IC, electromagnetic immunity plays a critical role towards evaluating the EMC performance to avoid the high cost of redesign. This paper focuses on the Direct Power Injection (DPI) immunity of processor chips with different external double data rate3 (DDR3) synchronous dynamic random access memory (SDRAM) in consumer electronics. To complete the DPI test, a test board complying with the standard IEC62132-4 and a dedicated test code have been designed. The effect of DC power injection interference on same DDR model but different DDR pins and the same DDR pin but different DDR models were analysed, the results can be used to locate the system-level EMC issues and optimize the design.

A new multitime programmable non-volatile memory cell using high voltage NMOS

A new multitime programmable (MTP) non-volatile memory (NVM) cell using high voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high voltage NMOS is used for selecting the memory cell. The memory cell has fewer number of transistors and terminals compared with the typical conventional memory cell. This reduces the area consumption and simplifies the implementation of memorys external circuit. In addition, the subthreshold swing (SS) of the memory cell is improved for larger coupling ratio. Experimental investigation on transfer characteristics, endurance, retention, and threshold voltage VTH shift and leakage current of the high voltage NMOS of the memory cell are presented. The experimental endurance behaviour of the proposed memory cell is superior to the conventional memory cell.

Investigations on the EFT immunity of microcontrollers with different architectures

Abstract With the development of MCUs and the deterioration of the electromagnetic environment, it has led microcontroller unit (MCU) electromagnetic susceptibility (EMS) to transient burst interference to become the focus on academics and enterprises. Most electromagnetic compatibility (EMC) studies of MCUs have not taken into account the contrasting nature of differing architectures. Subsequently, different MCU architectures may possess varying physical parameters, often resulting in different susceptibility EMI outcomes. This paper shall focus on the relationship between MCU architectures and its EMC susceptibility. Upon close examination, test results have shown to exhibit variances in relation to the two types of MCU architectures with regards to susceptibility of electrical fast transients (EFT) burst. Consequently, the underlying reasons resulting in MCU susceptibility variations based on differing MCU architectures shall also be elaborated on further.

Modelling of initial fast charge loss mechanism for logic embedded non-volatile memories

Abstract An analytical model of the initial fast charge loss mechanism for the logic embedded non-volatile memory (eNVM) is proposed in this paper for the first time. The charge loss phenomenon is caused by the contact-etch-stop-layer (CESL) capacitive effect, which screens part of the charge in the floating gate of the memory cell. Empirical equations are proposed to describe the formation process of the CESL capacitive effect, and the proposed model fits the experimental results excellently including the temperature dependence. The new model will be very helpful for the designers to accurately predict the memorys data retention capability. Furthermore, it can also be used to improve the initial fast charge loss of the logic eNVM.

The total ionizing dose response of a DSOI 4Kb SRAM

Abstract A 4xa0K-bit SRAM with 0.2xa0um Double Fully-Depleted Silicon-On-Insulator (DSOI) CMOS process is designed to examine circuit total ionizing dose (TID) and the back gate bias effect. Preview researches show that MOSFET electrical parameter shift due to TID damage can be compensated by back gate bias of the FDSOI technology. We can control the NMOS/PMOS back gate separately and discretionarily with DSOI structure which could improve circuit radiation tolerance. TID experiment results show that the total ionizing dose capability of the 4xa0Kb SRAM test chip is above 1xa0M rad (Si).

Characterization of change in microcontroller susceptibility during accelerated aging

With the increase of component density and decrease of operating voltage, microcontroller has become increasingly sensitive to electromagnetic interference (EMI), a low current or voltage interference coupled into microcontroller via pins could cause operating failure, or even damaged. Most electromagnetic compatibility (EMC) studies of microcontroller did not take the effects of aging into account. However, component aging can degrade the physical parameters of semiconductor and can change the immunity to EMI. This paper analyses the drift of microcontroller immunity to electrical fast transients (EFT) interference after accelerated aging. The measurements that show the variations in the test results for immunity reveal increasing susceptibility after temperature accelerated aging.

Investigation on EFT effects in a low dropout voltage regulator

This paper analyses the electrical fast transient (EFT) immunity level of a low dropout voltage regulator (LDO), with both measuring and modeling methods presented. Through non-synchronous transient injection method, the working states and fail models of the device under test (DUT) is depicted by monitoring the input and output conditions. The measurement results demonstrate that transient pulses with several tens of volts are aroused on the output port induced by the conducted EFT disturbances superimposed on power port. Injection probes, discrete components on the test board and power distribution network (PDN) of the chip are modeled based on impedance measurement. Simulation of the whole model contains passive and active effect components are compared with measurement results. Good agreement between simulation and measurement verifies the validity of the method proposed in this paper. Fail mechanism inside the chip and effects contributing of different components are discussed in general.