Jaakko Salonen
VTT Technical Research Centre of Finland
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Medical Imaging 1998: Physics of Medical Imaging | 1998
Konstantinos Spartiotis; R. Orava; Tom Schulman; Jouni Ilari Pyyhtia; Militiadis E. Sarakinos; Bal Sanghera; Agamemnon Epenetos; Ilkka Sunni; Jaakko Salonen; Leif Grönberg; Paivi Majander; David J. Allison; Melvyn J. Myers
We present an update on a novel direct digital X-ray imaging device and system. The system comprises a mosaic of hybrid solid state semiconductor devices removably mount onto a master plane covering an imaging surface of any desirable shape and size. Each imaging device comprises a pixel semiconductor detector flip-chip joined to a CMOS ASIC. Monolithic CdZnTe and Si pixel detectors with dimensions 12.2 X 4.2 mm2 and 18.9 X 9.6 mm2 have been implemented with a pixel pitch of 35 micrometer. Each circuit on the ASIC, corresponding to a detector pixel, is capable of accumulating thousands of X-rays in the diagnostic energy spectrum with high efficiency (CdZnTe) and user accumulation times ranging from just a few ms to a few s. Individual, removable tiles are combined in a mosaic providing continuous large area imaging with no inactive regions. This tiling approach allows for cost efficient replacement of defective tiles. The packaging delivers a compact, lightweight, portable cassette whose thickness is around 2.0 cm. The basic hybrid detector design and tiling scheme are generic and may be used in mammography, conventional radiography and fluoroscopy. A special tiling scheme has been designed for use in intraoral imaging. We present our measured Modulation Transfer Function (MTF) and Detective Quantum Efficiency (DQE). Images taken with hard objects, phantoms and soft tissue further demonstrate system functionality and provide a comparison with radiographic film and CR plates. The first application of the new technology is intended for the field of dental imaging, mammographic biopsy and other small area medical applications (approximately 10 - 30 cm2 imaging area) as well as Small Area Non Destructive Testing.
nuclear science symposium and medical imaging conference | 2010
Hannele Heikkinen; Akiko Gädda; Jaakko Salonen; Philippe Monnoyer; L. Tlustos; M. Campbell
The article describes a low temperature bump bonding process to assemble CdTe sensors to readout chips. The solder material used is In-Sn with a theoretical melting point of 118 °C. The solder was tested using Timepix readout chips with 30-μm diameter bumps and a 55-μm pitch bonded to CdTe sensors. The first results from these assemblies show very good bumping and bonding yield.
Journal of Micromechanics and Microengineering | 2011
Pradeep Dixit; Jaakko Salonen; Harri Pohjonen; Philippe Monnoyer
In this paper, we report a simple and cost-effective technique to fabricate a partially electroplated tapered through-silicon via (TSV) and redistribution line (RDL)-like structures on the field in a single process step using dry laminated photoresists. An array of 100 µm deep positively tapered silicon vias was etched by a three-step non-Bosch plasma etching process. Insulation, diffusion barrier and seed layers were deposited by low-temperature plasma-enhanced chemical vapor deposition and sputtering processes, respectively. A 15 µm thick dry MXA115 photoresist was laminated on the wafer by a roller-less vacuum lamination process. The dry resist allows a satisfactory patterning of the RDL-like structures by eliminating the chances of resist residuals falling in the etched TSVs. Direct-current (dc) electroplating was used to deposit 10 µm thick copper layers on the via sidewalls as well as on the field. Therefore, the electroplating not only partially fills the vias but also forms the RDL structures at the same time. Since both TSVs and RDLs are fabricated together in a single process step, several conventional process steps such as over-burden polishing, lithography, and metal etching were avoided. Compared to the conventional TSV fabrication processes, this dry resist lithography-based method turned out to be simple and very cost-effective in making complex TSV interconnects.
ieee nuclear science symposium | 2011
Hannele Heikkinen; Akiko Gädda; Sami Vähänen; Jaakko Salonen; Philippe Monnoyer; G Blaj; L. Tlustos; M. Campbell
The article describes a low temperature bump bonding process to flip chip bond CdTe sensors on Timepix readout chips with two separate pixel pitches: 55 µm and 110 µm. Because the sensor properties of CdTe start to degrade around 150 °C, InSn (48–52) solder joints were used. The solder bumping process flow and flip chip bonding routine are described, and leakage currents and radiation images are compared at different pitches. The results show low leakage currents and a good bump bonding yield with both pitches.
Journal of Instrumentation | 2014
Xiaopeng Wu; Pasi Kostamo; Akiko Gädda; Seppo Nenonen; Tommi Riekkinen; J. Härkönen; Jaakko Salonen; Hans Andersson; Yuri Zhilyaev; Leonid Fedorov; Simo Eränen; Marco Mattila; H. Lipsanen; Mika Prunnila; Juha Kalliopuska; Aarne Oja
Epitaxial GaAs material shows a great potential in X-ray spectroscopy and radiography applications due to its high absorption efficiency and low defect density. Fabrication of pixel radiation detectors from high-purtity epitaxial GaAs has been developed further. The process is based on mesa etching for pixellisation and sputtering for metallization. The leakage currents of processed pad detectors are below 10 nA/cm2 at a reverse bias of 100 V and decrease exponentially with the temperature. Measurement with transient current technique (TCT) shows that electrons have a trapping time of 8 ns. Good spectroscopic result were obtained from both a pad detector and a hybridized Medipix GaAs detector.
international microsystems, packaging, assembly and circuits technology conference | 2013
Pradeep Dixit; Heikki Viljanen; Jaakko Salonen; Tommi Suni; Jyrki Molarius; Philippe Monnoyer
The fabrication, electrical characterization and reliability study of copper through-silicon via (TSV) is reported. All the fabrication steps needed in this process have a process temperature <; 250°C. The copper TSVs have two distinct features: tapered via profile and partial filling of the vias. Besides the single Kelvin cell TSVs, daisy chains having up to 1400 TSVs were also fabricated and characterized. The measured electrical resistance of a single Kelvin TSV was between 3-10 MÛ. Later, these partially filled TSVs were subjected to various thermal and electrical cycling tests to study their behavior under different stress conditions. Electrical resistance of these TSVs was found to be stable under these tests; however certain TSV failure were also observed. Preliminary study has shown that via etching and via-filling related defects were the main reasons behind these failures. These cost-effective TSVs were implemented in the wafer level capping of MEMS resonators.
ieee nuclear science symposium | 1996
David J. Allison; A. Epenetos; P. Jalas; Z. Karim; M. Myers; R. Orava; Jouni Ilari Pyyhtia; Jaakko Salonen; B. Sanghera; M. Sarakinos; Tom Schulman; K. Spartiotis; I. Suni; C. Tieliang
We are presenting clinical images (objects, mammography phantoms, dental phantoms, dead animals) and data from a novel X-ray imaging device and system. The device comprises a pixel semiconductor detector flip-chip joined to an ASIC circuit. CdZnTe and Si pixel detectors with dimensions of the order of 1 cm/sup 2/ have been implemented with a pixel pitch of 35 /spl mu/m. Individual detectors comprise, therefore, tens of thousands of pixels. A novel ASIC accumulates charge created from directly absorbed X-rays impinging on the detector. Each circuit on the ASIC, corresponding to a detector pixel, is capable of accumulating thousands of X-rays in the energy spectrum from a few to hundreds of keV with high efficiency (CdZnTe). Image (X-ray) accumulation times are user controlled and range from just a few to hundreds of ms. Image frame updates are also user controlled and can be provided as fast as every 20 ms, thus offering the possibility of real time imaging. The total thickness of an individual imaging the including the mounting support does not exceed 4 mm. Individual imaging tiles are combined in a mosaic providing an imaging system with any desired shape and useful active area. The mosaic allows for cost effective replacement of individual tiles. A scanning system, allows for elimination, in the final image, of any inactive space between the imaging tiles without use of software interpolation techniques. The Si version of our system has an MTF of 20% at 14 1p/mm and the CdZnTe version an MTF of 15% at 10 1p/mm. Our digital imaging devices and systems are intended for use in X-ray and gamma-ray imaging for medical diagnosis in a variety of applications ranging from conventional projection X-ray imaging and mammography to fluoroscopy and CT scanning. Similarly, the technology is intended for use in non destructive testing, product quality control and real time on-line monitoring. The advantages over existing X-ray digital imaging modalities (such as digital imaging plates, scintillating screens coupled to CCDs etc.) include compactness, direct X-ray conversion to an immediate real time digital display, exquisite image resolution, dose reduction and large continuous imaging areas. Our measurements and images confirm that this new digital imaging system compares favourably to photoluminescence.
international microsystems, packaging, assembly and circuits technology conference | 2012
Pradeep Dixit; Sami Vähänen; Jaakko Salonen; Philippe Monnoyer
This article report a continuous plasma etching process using SF6/O2/Ar gases for fabricating 100 μm deep tapered through-silicon vias (TSV). The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70° to 85° and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F* radicals, passivation film by O2, and ion-assisted passivation etching. The flow rates of SF6 and O2 were found to be the important factors which determine the profile angle and via surface roughness. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 μm deep vias having a profile angle of 83°. Insulation and seed layers were deposited by conventional low-temperature processes. The tapered vias were then partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 mΩ for the majority of the TSVs.
Archive | 1997
Konstantinos Evangelos Spartiotis; Jaakko Salonen
Archive | 1997
Konstantinos Evangelos Spartiotis; Jaakko Salonen