Sami Vähänen

Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 µm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 Ω. The electrical resistance was varying from 60 Ω to 90 Ω for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements.

Analysis of microstructural evolution in SLID-bonding used for hermetic encapsulation of MEMS devices

The need for reliable hermetic sealing of electronic components has arisen along the increasing popularity of silicon based Micro Electro Mechanical Systems (MEMS). In this paper we have analyzed the formation and evolution interconnections made with Solid Liquid Interdiffusion (SLID) bonding by utilizing thermodynamic-kinetic method. The analysis of the phase transformations and consequent formation of stresses in Au-Sn system during bonding as well as the remelting temperatures of the Au-In-Sn interconnections can be carried out with the help of thermodynamic equilibrium diagrams. In addition, by combining qualitative thermodynamic calculations with qualitative kinetic considerations the evolution of interfacial microstructures between Ni contact metallization and the Au-Sn bonding alloy was predicted.

Low-temperature bump bonding of Timepix readout chips and CdTe sensors at Different Sensor pitches

The article describes a low temperature bump bonding process to flip chip bond CdTe sensors on Timepix readout chips with two separate pixel pitches: 55 µm and 110 µm. Because the sensor properties of CdTe start to degrade around 150 °C, InSn (48–52) solder joints were used. The solder bumping process flow and flip chip bonding routine are described, and leakage currents and radiation images are compared at different pitches. The results show low leakage currents and a good bump bonding yield with both pitches.

The influence of edge effects on the detection properties of cadmium telluride

Driven by the demand of various applications for a detection area that is larger than the active area of a single detector module, we explore the possibility to realise a large-area detector by a seamless tessellation of multiple detectors. This requires sensors with a minimum amount of dead area at the edge. In order to be able to reduce this area, edge effects must be understood and avoided or mitigated. In this paper, we report on first tests that are performed on diamond-blade diced slim-edge pieces of cadmium telluride with a last-pixel-to-edge distance of only 65 µm. The results indicate that the edge-pixel response is not significantly affected with respect to the leakage current and the charge collection efficiency. First measurements towards a quantification of the detective quantum efficiency have been made on edge pixels by determining the pixel response function and the noise power spectrum.

Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps.

Role of process gases in making tapered through-silicon vias for 3D MEMS packaging

This article report a continuous plasma etching process using SF6/O2/Ar gases for fabricating 100 μm deep tapered through-silicon vias (TSV). The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70° to 85° and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F* radicals, passivation film by O2, and ion-assisted passivation etching. The flow rates of SF6 and O2 were found to be the important factors which determine the profile angle and via surface roughness. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 μm deep vias having a profile angle of 83°. Insulation and seed layers were deposited by conventional low-temperature processes. The tapered vias were then partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 mΩ for the majority of the TSVs.