Jaap Bisschop

Effect of thermal gradients on the electromigration life-time in power electronics

The combined effects of electromigration and thermomigration are studied. Significantly shorter electromigration lifetimes are observed in the presence of a temperature gradient. This cannot be explained by thermomigration only, but is attributed to the effect of temperature gradient on electromigration-induced failures.

Fast temperature cycling and electromigration induced thin film cracking multilevel interconnection: experiments and modeling

There is an increasing reliability concern of thermal stress-induced and electromigration-induced failures in multilevel interconnections in recent years. This paper reports our investigations of thinfilm cracking of a multilevel interconnect due to fast temperature cycling and electromigration stresses. The fast temperature cycling tests have been performed in three temperature cycle ranges. The failure times aare represented well by a Weibull distribution. The distributions are relatively well behaved with generally similar slope (shape factor). The failure mechanism is well fitted by the Coffin-Manson equation indicating a uniform acceleration. The observation of cracking in the interlayre dielectric due to fast temperature cycling stress from failure analysis agrees well with the failure mechanism modeling and the calculated Coffin-Manson exponent. Electromigration experiments have shown that devices failed due to extrusion-shorts without increasing of resistance of metal line. The failure times are represented better by the Weibull distribution than by the lognormal distribution (normally used for electromigration data). A simulation of stress buil-up in metal line using an electromigration simulator confirmed that the cracking of interlayer dielectric is the weakest spot and most likely to cause electromigration failure.

The Relation Between Degradation Under DC and RF Stress Conditions

In this paper, we develop a method to derive degradation formulas for time-varying stress from the formulas for the constant-bias case, discuss its limitations, and apply it to a set of radio-frequency (RF) stress experiments. First, we will give a new derivation of the well-known power-law case without invoking any specific physical degradation model. Next, we will show that this derivation can be generalized to the broader class of degradation functions of type g(f(Vi)·t). We will illustrate our work with an example of hot-carrier degradation in 45-nm n-channel metal-oxide-semiconductor field-effect transistors, where an accurate prediction of the measured lifetime under RF stress conditions is obtained from the measured degradation under direct-current stress.

The hot carrier degradation rate under AC stress

In this work the methodology used for predicting hot carrier device degradation under AC stressing conditions is critically re-examined. Having an accurate method is a key prerequisite of developing useful tools for the reliability simulation of any circuit. It will be shown that existing methods are not generally applicable. A new, better applicable method is presented and verified with experimental data.

Effect of metal layout design on passivation crack occurrence using both experimental and simulation techniques

Thermo-mechanical reliability is one of the concerns for semiconductor developments due to miniaturization, introduction of new materials, and higher application temperatures. FE modeling techniques are developed to predict the effect of IC interconnect metal designs on the thermo-mechanically-induced cracking of passivation layers. Experimental techniques on specially designed IC packages are developed to verify the predicted passivation cracks. With the verified 2D and 3D models, various simulations are performed and it is established that delamination of the IC/compound interface is a key trigger for passivation cracking. When delamination is present, crack occurrence is found to depend on the metal layout and location on the IC. Optimizing the metal layout design can even prevent passivation cracks. By combining efficient and accurate simulations with a limited number of experiments, passivation cracks can be quantitatively predicted prior to physical prototyping.

Reliability methods and standards

Abstract This tutorial focuses on three aspects of standardization: existing standards and organizations, evolution of standards and creation of new standards, new developments. An overview of existing standards and involved organizations is given. The main standardization institutes and forums for semiconductor reliability are described. The process of introducing new standards and changes is described. New and changed standards are needed when technologies change and when increased knowledge leads to better methods. Also, new application areas and changed customer requirements may lead to changed or new methods. Advantages and disadvantages of standards are discussed, with emphasis on standards for qualification. Development and use of knowledge-based methods is addressed.

Simulating NBTI Degradation in Arbitrary Stressed Analog/ Mixed-Signal Environments

A compact negative bias temperature instability (NBTI) model is presented by iteratively solving the RD equations in a simple way. The new compact model can handle arbitrary stress conditions without solving time-consuming equations, and is hence, suitable for analogue/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of ageing into account. The simulation speed has increased at least a thousand times compared to classical RD models. The performance of the model has been validated by both RD theoretical solutions and 140-nm CMOS silicon measurement.

Determination of the stress level for voltage screen of integrated circuits

Abstract Voltage screen is a method to screen out products that suffer from defectivity related issues. A risk associated with voltage screen is that the applied voltage is too severe and damages the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without taking into account the particularities and the knowledge of the specific process. This paper describes a general approach to determine a safe level for voltage screening of products. In this approach, the onset of the wearout phase is not allowed to shift more than 1%. All the information needed to determine the voltage value is in general typically available from the process reliability tests performed as part of the process qualification.

Impact of IC wafer fab and assembly fab processes on package stress induced product reliability issues - an insight into the package stress relief design rules by simulation

In this work the impact of the layout of the top metal of the integrated circuit (IC) and the most relevant process and material parameters of IC wafer fab and assembly fab on package stress induced damages to the ICs during temperature cycling is studied by means of thermo-mechanical simulations with experimental verifications. Besides die size, the materials for passivation, silicon thickness, molding compound properties, the cohesion between the molding compound and the die surface, and lead frame yield stress, all are found to significantly influence the risk of damages or failures on the IC surface. The results suggest a more complete package stress relief design rule, pointing to a systematic approach to eliminate or suppress the package stress induced damages to the IC and consequently a possibly more efficient use of the silicon area in IC design.