Jacek Flak

Template Design for Cellular Nonlinear Networks With 1-Bit Weights

In this paper, we show how a cellular nonlinear network with 1-bit weight programmability can be used for processing black and white image data. When using such a binary-programmable network, some templates need to be processed algorithmically, in other words, divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give guidelines as to how the division into subtasks (when applicable) is performed. A large collection of templates suitable for the proposed model is shown. We also describe one possible cell structure that realizes the binary-programmable model. The cell is modeled with Matlab and selected template simulations are shown.

Dense CMOS implementation of a binary‐programmable cellular neural network

An implementation of a cellular neural/non-linear network (CNN) for processing black-and-white (B/W) images is presented in which the template terms are 1-bit programmable. Such approach leads to a very compact implementation of the coefficient circuits and fast (digital) programming. In this programming scheme, the more complex templates are split into subtasks that are run successively. The structure allows a direct or algorithmic evaluation of the majority of templates proposed for B/W images. The transient mask is utilized in performing the local logic operations as well as in template operations. The proposed architecture is suitable for high-density implementations. A test structure of a 4 × 4 network has been implemented with a standard digital 0.18-µm CMOS process. One cell occupies only 155 µm2, making possible the implementations of very large networks on a single chip. The algorithms used for the logic function computations and selected template evaluations are described, and the corresponding measurement results are shown. Copyright

Template design for binary-programmable cellular nonlinear networks

In this paper we show how a binary-programmable cellular nonlinear network can be used for processing black and white templates. When using a binary-programmable network, some templates need to be divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give general rules as to how the division into subtasks is performed. We also show a cell structure that realizes the binary-programmable model. The cell is modeled with Matlab and selected template simulations are shown.

Programmable CNN cell based on SET transistors

This paper presents a neuron structure that resembles the basic McCulloch and Pitts model and is suitable for an implementation with single-electron tunneling (SET) transistors only or as a SET/FET hybrid. It combines a basic neuron with nine binary-programmable synapses and a programmable bias term. With these synaptic inputs the neuron is suitable for building a processing array like the cellular neural network (CNN) for processing black and white (BAY) images. The binary programming scheme is fast and robust, and thus it can be applied to architectures based on nanodevices. The cell structure and operation principles are described and illustrated by simulation results

High density VLSI implementation of a bipolar CNN with reduced programmability

In this paper a VLSI implementation of a bipolar CNN with a reduced programmability is described. The programmability of the weights and the bias term is reduced to one bit. Since the programming is digital, the template write time is fast. While losing some generality in the programming, the cell array is still able to perform most of the bipolar CNN templates presented so far. The proposed structure yields a very compact realization in a dense layout. The cell size using a 0.18/spl mu/m digital CMOS process was 155/spl mu/m/sup 2/.

Scalable fault-tolerant logic system based on regular array of locally interconnected gates

This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.

FG-MOS neuron for binary CNN

This paper presents a neuron implementation based on floating-gate MOSFET (FG-MOS) structure. The computation is performed by charge distribution at the input of FG-MOS inverter determining the cell state. There is no current-flow through the interconnections after processing is completed, thus a significant reduction in DC power consumption can be achieved. Such neuron can be used to build a capacitively coupled cellular neural/nonlinear network (CNN) for processing black and white (B/W) images. Although the coupling coefficients are basically implemented with capacitances, this approach provides them with 1-bit programmability. Also the neurons threshold level can be digitally programmed to four different values. The templates operating on the B/W images can be modified to have only binary-valued {0,1} terms or can be split into such (sequentially run) simple subtasks. Therefore, the presented neuron structure is able to perform the evaluation of almost all B/W templates proposed so far. Exploration of FG-MOS structures can help to understand the implementation problems of capacitively coupled CNNs. Such a situation appears, e.g., in nanoelectronic CNNs composed of single-electron tunneling (SET) transistors, which also deal with B/W images only. Moreover, the binary programmability approach utilized here should help to develop an effective programming scheme for future SET or CMOS-SET hybrid CNN implementations. Along with the neuron structure, its operation description and simulation results of the 8 x 8 network are presented.

Fault-tolerant architecture for nanoelectronic digital logic

This paper presents a new system architecture for implementing fault-tolerant information processing. The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices. Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility. The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.

On emerging nanodevices and architectures

A general review of the most promising nanodevices is presented with a special focus on their advantageous properties as well as use limitations. In addition, two architectures suitable for implementing nanostructures are described

Binary cellular neural/nonlinear network with programmable floating-gate neurons

This paper presents an implementation of a cellular neural/nonlinear network (CNN) with capacitively coupled neurons that are based on the floating-gate MOSFET (FG-MOS) technology. The circuit is intended for processing black and white (B/W) images. A neuron state is determined by charge distribution in the input of a FG-MOS inverter. The capacitive couplings to the neighbors are one-bit programmable, while the bias template can be programmed with two bits. Also, a fixed state map (transient mask) is included in the cell. The operation of an 8/spl times/8 network is illustrated by simulations of selected templates.