Mika Laiho

Stateful implication logic with memristors

In this paper computation with memristors is studied in terms of how many memristors are needed to perform a given logic operation. It has been shown that memristors are naturally suited for performing implication logic (combination of implication and false operation) instead of Boolean logic. Also, it should be noted that a memristor can be used as both a logic gate and a latch (stateful logic). Being functionally complete, implication logic can be used to compute any Boolean function. However, by performing implication logic with stateful devices, storage of intermediate results requires additional memristors to keep data yet to be used from being written over. This paper describes an effective way to compute any Boolean function with a small number of memristors. Also, the length of the corresponding computing sequence is considered.

A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.13- BiCMOS process is presented. The sensor interface consists of a front-end that converts the acceleration signal to voltage, two algorithmic ADCs, two frequency references, and a voltage, current, and temperature reference circuit. Die area and power dissipation are reduced by using time-multiplexed sampling and varying duty cycles down to 0.3%. The chip with a 0.51 active area draws 62 from a 1.8 V supply while sampling temperature at 100 Hz, and four proof masses, each at 1.04 kHz. With a 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 482 , 639 , and 662 , respectively.

Reducing the feature vector length in local binary pattern based face recognition

In this paper we propose a method for reducing the length of the feature vectors in the local binary pattern (LBP) based face recognition. This is done to speed up the matching of the feature vectors in real-time face recognition and detection systems. We define a new discrimination concept of the uniform local binary patterns called symmetry. Patterns are assigned different levels of symmetry based on the number of ones or zeros they contain. These symmetry levels are rotation invariant allowing a general discrimination methodology. Empirical studies on both human perception and LBP face recognition accuracy using the standard FERET database confirm that the concept of symmetry is an efficient discriminator.

Cellular nanoscale network cell with memristors for local implication logic and synapses

This paper describes a cellular nanoscale network cell structure that is aimed to be built as a CMOS-nanomemristor hybrid. The processing cell uses memristors as ON-OFF programmable synapses, local logic and memory. Local logic is based on memristor computations using material implication. Only 15 CMOS transistors per cell are used, independent of the size of the neighborhood, since memristors are used as synapses. Also, space-dependent templates (weight matrices) are possible at no extra hardware cost. The operation of the cell is described and simulation results are shown to illustrate the operation.

On Synthesis of Boolean Expressions for Memristive Devices Using Sequential Implication Logic

We determine an explicit procedure for representing any Boolean expression in a recursive form which can be realized using memristive devices, and demonstrate how the truth value of any Boolean expression can be determined using no more than two computing memristive devices. We present an algorithm which can be used to significantly reduce the number of implications required for representing a specific Boolean expression, and consider device-specific benefits in terms of reducing the lengths of computational sequences.

Arithmetic operations within memristor-based analog memory

This paper describes how memristors could be used as an analog memory and computing elements. The key idea is to apply comparison and programming phases cyclically so that the memristor can be programmed to a given conductance level at a fixed voltage. It is further described how the cyclical programming could be used in computing. A configuration needed to copy the sum of conductances of two memristors into a third one is described. It is further shown how the devices could be configured so that addition and subtraction of positive and negative analog conductances could be performed. The presented memory structure requires a memristor model with a nonlinear programming sensitivity (programming threshold) for proper programming selectivity. A model of such a memristor is shown and key simulations are presented.

Implication logic synthesis methods for memristors

We propose three new synthesis methods for memristive implication logic and compare these with each other and with a basic method which was originally proposed in [5]. The results show that by using complementary representation of variables and multi-input operation, the lengths of computational sequences required for computing a given Boolean function are significantly reduced; for the three-input parity function this reduction is approximately 85 percent compared to the basic method.

Applications and limitations of memristive implication logic

In its elementary form, memristive implication logic suffers from multiple disadvantages such as the lengths of the computational sequences required to synthesize a Boolean function, the lack of fan-out, and the requirement of complex control signals. In this paper we present a new stateful logic operation available for rectifying memristors which corresponds to the logical operation known as the converse nonimplication, and show that it solves the fan-out problem. Moreover, we show how parallel stateful logic can be performed within a CMOL memory architecture, and how it can be used to shorten the computational sequences. We also discuss applications where stateful logic could be advantageous when compared to more conventional solutions.

Large-Scale Memristive Associative Memories

Associative memories, in contrast to conventional address-based memories, are inherently fault-tolerant and allow retrieval of data based on partial search information. This paper considers the possibility of implementing large-scale associative memories through memristive devices jointly with CMOS circuitry. An advantage of a memristive associative memory is that the memory elements are located physically above the CMOS layer, which yields more die area for the processing elements realized in CMOS. This allows for high-capacity memories even while using an older CMOS technology, as the capacity of the memory depends more on the feature size of the memristive crossbar than on that of the CMOS components. In this paper, we propose the memristive implementations, and present simulations and error analysis of the autoassociative content-addressable memory, the Willshaw memory, and the sparse distributed memory. Furthermore, we present a CMOS cell that can be used to implement the proposed memory architectures.

A cellular computing architecture for parallel memristive stateful logic

We present a cellular memristive stateful logic computing architecture and demonstrate its operation with computational examples such as vectorized XOR, circular shift, and content-addressable memory. The considered architecture can perform parallel elementary memristor programming and stateful logic operations, namely implication and converse nonimplication. The topology of the crossbar structure used for computing can be dynamically reconfigured, enabling combinations of local and global operations with varying granularity. In the CMOS cells used for controlling the memristors, we apply a new type of capacitive keeper circuit, which allows for energy efficient implementation of logic operations. The correct operation of this architecture is verified by detailed HSPICE simulations for a structure containing eight memristive crossbars. This work presents a hardware platform which enables future work on parallel stateful computing.