Jacek G. Smolinski

Model-based verification for first time right manufacturing

In this paper we will describe the implementation of a system for model-based verification of post OPC data into a manufacturing data flow. Verification is run automatically, upon OPC completion, on the critical levels for every chip run in the 130nm node and beyond to ensure that OPC errors are caught before hardware is committed in the manufacturing line. The checks are derived from the design rule manual, and are written to cover the intent of the design rules. Some of the challenges of implementing a robust model-based verification solution for manufacturing will be discussed, including resource requirements, data management, cycle time, and the creation of a closed loop system to ensure that verification is completed on all chips. The benefits of implementing model-based verification include improved feedback to lithography and OPC teams, enabling constant improvement, as well as increasing the probability of first time right manufacturing of a new chip design.

High-resolution ultraviolet defect inspection of DAP (darkfield alternate phase) reticles

The manufacturing implementation of alternating aperture PSMs (AltPSM) has been gated by the impacts these techniques have on reticle manufacturing, specifically reticle defect inspection and repair. Die-to-die inspection techniques have been achieved for some clearfield multiphase alternate phase reticles, but the required die-to-database solutions are not currently available with defect inspection systems. In response to these mask manufacturing issues and IC design layout issues, resolution enhancing techniques based on Darkfield Alternate Phase (DAP) reticle designs are now of growing importance. A DAP Programmed Evaluation Reticle, DAPPER, was fabricated and inspected on a new high numerical aperture ultraviolet reticle inspection system. The results show reasonable defect sensitivity performance in the presence of both reticle geometry and quartz etch topography characteristic of 130-nm node advanced logic circuit DAP reticles.