Edward W. Conrad

Using advanced simulation to aid microlithography development

An early historical overview is first presented here on the use of simulation in optical microlithography, along with a description of the general physical models. This paper then turns to more recent development work in microlithography simulation, which has followed several very different tracts. Three of the most important areas are discussed here. The first involves improvements in the underlying physical models, such as advances beyond the Kirchhoff boundary condition in optical diffraction theory, as well as a deeper understanding into the chemistry and physical behavior of photoresist materials. Such work guides basic understanding both in the optics and photoresist areas. At the other extreme, phenomenological models are being advanced to enable simulation results on large scales to be placed in the hands of device and circuit designers. Finally, optimization of the large number of allowable parameters is a pervasive problem that has received much attention and interest by the engineering community.

Model-based verification for first time right manufacturing

In this paper we will describe the implementation of a system for model-based verification of post OPC data into a manufacturing data flow. Verification is run automatically, upon OPC completion, on the critical levels for every chip run in the 130nm node and beyond to ensure that OPC errors are caught before hardware is committed in the manufacturing line. The checks are derived from the design rule manual, and are written to cover the intent of the design rules. Some of the challenges of implementing a robust model-based verification solution for manufacturing will be discussed, including resource requirements, data management, cycle time, and the creation of a closed loop system to ensure that verification is completed on all chips. The benefits of implementing model-based verification include improved feedback to lithography and OPC teams, enabling constant improvement, as well as increasing the probability of first time right manufacturing of a new chip design.

Comparison of electromagnetic scattering measurements to simulation for microelectronic structures

We present an electromagnetic-based method that enables prediction of microlithographic structures of 100 nm and below, for analyzing manufacturability of next-generation microchip technology in real time, in situ. The method is robust, versatile, precise, and fast, and experimentally verified by using both scanning electron microscopy and atomic force microscopy.

A new method to obtain reproducible measurements on single-wavelength, single-angle-of-incidence, null-seeking, polarizer-compensator-sample-analyzer ellipsometers

Abstract A method is discussed which enables routine users of single-wavelength, single-angle-of-incidence, null-seeking polarizer-compensator-sample-analyzer ellipsometers to obtain reproducible measurement results on reasonably aligned production ellipsometers without tediously having to adjust and/or characterize them. This method is based on a numerical analysis, of data taken from a carefully prepared set of SiO 2 /Si samples, which determines a number of sample and null-seeking ellipsometer parameters. The method is shown to give results for ellipsometer alignment corrections equivalent to those obtained by standard, more tedious, procedures and it yields material parameters consistent with accepted values for the SiO 2 /Si system. Application of these results is demonstrated, including measurements on SRM-2530 standards obtained from the National Institute of Standards and Technology. We also propose that the error term, which is used in our numerical analysis to characterize the ellipsometer, should be used routinely as a gauge of the combined measurement and model errors for all samples that are measured.

Electrical validation of through-process optical proximity correction verification limits

Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.

Electrical Validation of Through Process OPC Verification Limits

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

Validating optical proximity correction with models, masks, and wafers

Complex Optical Proximity Correction (OPC) must be deployed to meet advanced lithography requirements. The OPC models are used to convert input design shapes into mask data that often deviate significantly from both the initial design and the final wafer image in resist. The process includes selective shape biasing, applying pattern-specific corrections, and, possibly, modeling the effect at multiple exposure conditions. It is important to verify the results of the OPC model and this is done by invoking OPC verification programs. The verification models identify points of failure to specific criteria. Failure can be defined as the simulated resist dimension below which a feature will not survive additional processing. Since these models are built for use in OPC verification, they may only be well-calibrated at feature sizes near target. This can introduce uncertainties in the failure predictions. This paper will explore options for validating the OPC verification models and methods. While wafer prints are an obvious source of feedback on the simulated results, there are also options at mask level. In this paper, we study the effect of programmed defects at wafer level, mask level and through OPC verification method. For each test case, five points in the process window space are chosen to provide comparison data between OPC verification measurements, mask-level intensity contour measurements - e.g. Aerial Image Microscope System (AIMS), and wafer measurement of patterned photoresist. The results permit correlation to measurable metrics and provide an improved understanding of OPC verification validity.