Jack Glas

A CMOS GSM IF-sampling circuit with reduced in-channel aliasing

A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-/spl mu/m CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.

Testing the double low-IF receiver architecture

The purpose of this paper is to show through laboratory results, the performance of the new DLIF (double low-IF) receiver architecture. This new approach minimizes the receivers cost by eliminating the need for RF image-reject and IF-SAW channel filters, avoids some of the shortcomings of direct conversion and single low-IF methods and can be applied in GSM-like mobile stations. Performance results are presented in terms of the frame error rates and residual bit error rates and can thus be compared with GSM specifications.