Mihai Banu

Fully differential operational amplifiers with accurate output balancing

Design considerations are presented for attaining accurate output balancing in fully differential operational amplifiers over the useful operating frequency of the differential signals. Such output balancing is obtained by merging the common-mode feedback and the differential gain paths as close to the front end of the amplifier as possible, ensuring maximum sharing of circuit components. Two circuit designs implemented in a 5-V, 1.75- mu m process are presented, one based on a two-stage topology and one based on a folded cascode topology. Experimental results for both designs are given. >

A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers

We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-/spl mu/m CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented.

Low-power pipeline ADC for wireless LANs

In this paper, a 10-bit 40-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 12 mW was achieved by using a time-interleaved and pipelined architecture with shared operational amplifiers. This circuit was fabricated in a 2.5-V 0.25-/spl mu/m technology with metal-oxide-metal capacitors. Experimental results are within design ranges and are in good agreement with simulation data. It turns out that the proposed Nyquist-rate ADC provides a potential solution for low-power high-speed applications, e.g., wireless LANs.

MOS oscillators with multi-decade tuning range and gigahertz maximum speed

The author studies the realization of fully integrated MOS oscillators with multidecade tuning range and top speed exceeding 1 GHz. This fast operation requires the use of submicrometer fabrication technology. To overcome the analog circuit limitations of the latter, the design of the oscillator is simplified and, in turn, highly redundant digital and analog control capability is provided. A brief review of possible oscillator structures is given and it is found that the best approach for high-speed, wide-range specifications is the relaxation network of the constant-current charge type. Circuit techniques are presented to increase the speed of the latter, based on active use of parasitics and simplified feedback networks. NMOS and CMOS implementations are discussed and compared. The design and performance of an experimental submicrometer NMOS oscillator is presented. This device covers the 100-kHz-to-1-GHz frequency range and has a robust structure. >

150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Two 0.9 /spl mu/m CMOS chips serve for burst-mode clock and data recovery applications specific to passive optical network (PON) systems. In each case, a core, first order clock recovery circuit is realized by two gated ring oscillators, indirectly frequency-tuned by a phase-locked loop using a third replica oscillator and a local reference signal. Instantaneous phase locking is guaranteed by restarting the gated oscillators every time input data transitions occur. This method has been demonstrated to be precise enough to handle input data patterns containing hundreds of bits between transitions without errors. In addition, the circuit is small and dissipates low power. However, the recovered clock signal thus obtained inherits all jitter present in the input data signal. This shortcoming has been overcome in the present designs by two different methods. The results are the total elimination of jitter propagation and the generation of clean data and clock output signals. The first chip operates at 150 Mb/s. Since the data is demultiplexed into 8 channels, the local reference signal runs eight times slower than the transmission rate. This allows ample time for jitter-rejection processing. The second chip operates at 30 Mb/s without a demultiplexer. The jitter rejection is accomplished with an elastic store based on five 1 b registers.

A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications

The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at relatively low cost. Highlighted are the analog interface circuits of the two chips. These include a phase splitter and amplifier for the maser clock input, a precision 50- Omega output driver for high-speed synchronous-transport-signal-12 (STS-12) data, as well as input amplifier and an output stage for low-speed differential STS-1 data. >

LOW COST, LOW POWER DIGITAL OPTICAL RECEIVER MODULE FOR 50 Mb/s PASSIVE OPTICAL NETWORK

A low cost digital optical receiver module for passive optical networks was developed. In order to reduce the cost of the receiver module, ICs are packaged in low cost plastic packages and the receiver module is fabricated using conventional surface mount technology. The receiver module is capable of receiving burst and packet digital optical signals, and recovered data and recovered clock in CMOS logic level are available. The receiver module contains a connectorized InGaAs PIN photodiode, a burst/packet mode-compatible preamplifier IC in a 32-lead TQFP plastic package, a comparator IC in an 8-lead SOIC plastic package, a clock recovery IC in a 32-lead TQFP plastic package and other active and passive components. These components are mounted on a four-layer printed wiring board. The intrinsic minimum receivable optical signal power is around -42 dBm/Ave and the dynamic range is over 26 dB for BER 1 × 10-8 at a bit rate of up to 60 Mb/s. The total power consumption of this module is less than 200 mW.

Yannis Tsividis' Early Contributions to MOS Filters

In the 1970s, when the bipolar transistor was the undisputed king of analog integrated circuits (ICs), most electrical engineers regarded the MOS transistor as a second-rate device for ICs: it was a good switch, but a mediocre amplifier. As a graduate student at UC Berkeley, under the supervision of Paul Gray, Yannis Tsividis had a very different vision. He saw the MOS transistor as the future star for mixed-signal ICs and was excited to prove to the world he was right. The opening gambit was his thesis work demonstrating the first fully-integrated MOS opamp. This single achievement propelled him to the top of his generation of researchers and earned him a Berkeley PhD degree, a teaching appointment at Columbia University and a consulting position at Bell Laboratories.

A System Approach to Integrated Power Amplifier Analysis and Design

Numerous power amplifier circuits are described in the literature, which seem to follow many distinct design approaches. While circuit implementations may be quite different indeed, the underlining system-level signaling inside these circuits follows similar conditions dictated by the common design objective for high efficiency. This paper presents a general theory for analyzing and designing power amplifiers, providing an insight on the fundamental factors limiting the performance, irrespective of the implementation circuits or technology.

Design Techniques for Non-Oversampled, Instantaneously Locked Clock and Data Recovery Circuits - An Overview

Traditional narrow-band clock recovery circuits such as those based on LC tanks, SAW filters or PLLs suffer from the fundamental limitation of locking (reaching steady-state operation) slowly compared to the input data rate. This is inconsequential in classical digital links where phase-coherent data flows continuously. However, if data arrives in asynchronous packets, as it does in modern communication systems such as PON’s (Passive Optical Networks), long locking [times cause significant penalties in the transmission efficiency. For burst-mode applications new clock recovery methods with greater acquisition agility are needed.