Vladimir I. Prodanov

A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers

We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-/spl mu/m CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented.

A "divide and conquer" technique for implementing wide dynamic range continuous-time filters

This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation and chip area. The system provides undisturbed output during range switching, contrary to conventional automatic gain control (AGC)/filter arrangements that generate disturbances every time the gain of the AGC changes. We also report on a low-noise highly linear CMOS transconductor useful for high-frequency applications. A chip implementing the ideas of this paper was fabricated in a 0.25-/spl mu/m digital CMOS process. The intended application of the filter is channel selection in an 802.11a/Hiperlan2 Wireless Ethernet receiver. The chip dissipates 9 mA, occupies an area of 0.7 mm/sup 2/, and maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB over a 48-dB signal range, with good blocker immunity. This performance represents at least an order of magnitude improvement over existing channel selection filters, even those that do not achieve disturbance-free operation.

GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling

Thr authors introduce a serial passive clock distribution technique allowing efficient and accurate skew removal at any arbitrary clock drop point. The passive transmission medium may be on-chip electrical transmission lines built in current IC technology or possible optical waveguides in future developments. The proposed technique is naturally insensitive to practical loses and other non ideal effects and has the capability of covering large chip areas

New CMOS universal constant-Gm input stage

Conceptually new constant-Gm input-stage architecture is presented. It provides near constant net transconductance independent of transistor operating region-strong, moderate or weak inversion. One possible implementation of the proposed architecture is discussed in details. Its operation has been experimentally verified. Results from performed measurements are included.

7V tristate-capable output buffer implemented in standard 2.5 V CMOS process

This paper describes high-voltage CMOS buffer architecture that uses low-voltage transistors. The voltage capability of the presented architecture is nearly three times larger than the voltage capability of the used MOSFETs. This buffer topology could be used to provide 3.3 V compatibility of 1.2 V and 1.5 V digital ICs implemented in standard CMOS technology. A 7 V circuit-prototype was fabricated in 0.25 /spl mu/m 2.5 V CMOS technology. Performed measurements demonstrate stress-free operation in both active and high-impedance mode.

Robust high-pass and notch Gm-(grounded) C biquads: how many different topologies are there?

This paper deals with Gm-C biquadratic filters that use grounded capacitors. We derive all practical HP and notch filter topologies that do not require critical component matching. The aim of this derivation was to discover new architectures. The result of this derivation is quite unexpected: there are only three distinct topologies (one notch and: two high-pass). None of them is particularly new because all reported in the literature biquad circuits are their embodiments.

V-I converters with transconductance proportional to bias current in any technology

In this paper we discuss circuits comprised of multiple differential pairs driven in parallel. We show that high linearity and linear with bias current tunability are intrinsic properties of any equidistant-offset multi-pair circuit. We argue that these two properties could potentially allow us to implement designs of analog filters, multipliers and other circuits that are (in first-order) technology independent. Simulations results are provided in support of presented simple intuitive explanation.

A System Approach to Integrated Power Amplifier Analysis and Design

Numerous power amplifier circuits are described in the literature, which seem to follow many distinct design approaches. While circuit implementations may be quite different indeed, the underlining system-level signaling inside these circuits follows similar conditions dictated by the common design objective for high efficiency. This paper presents a general theory for analyzing and designing power amplifiers, providing an insight on the fundamental factors limiting the performance, irrespective of the implementation circuits or technology.