Jack Yeh

Method to increase coupling ratio of source to floating gate in split-gate flash

Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate

Vertical split gate field effect transistor (FET) device

Method of forming a floating gate self-aligned to STI on EEPROM

Method of making the selection gate in a split-gate flash EEPROM cell and its structure

Method to fabricate poly tip in split-gate flash

Logic compatible storage device

Process of forming an EEPROM device having a split gate

Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash

Method to avoid program disturb and allow shrinking the cell size in split gate flash memory