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Featured researches published by Di-Son Kuo.


Semiconductor Science and Technology | 1999

Influence of source coupling on the programming and degradation mechanisms of split-gate flash memory devices

Kuo-Ching Huang; Yean-Kuen Fang; Dun-Nian Yaung; Chin-Ying Chen; Hung-Cheng Sung; Di-Son Kuo; Chung-Shu Wang; Mong-Song Liang

In this paper, the mechanism of programming operation considering the source-to-floating gate coupling ratio (SCR) in split-gate source-side injected flash memory has been discussed and experimentally demonstrated. The effects of SCR on the programming performance and cycling endurance have also been investigated in detail. The experimental results indicate that the cell with higher SCR possesses a higher programming speed. Under the same programming speed, the higher-SCR cell shows larger cycling endurance compared to lower-SCR cell.


Solid-state Electronics | 2001

A novel programming technique for highly scalable and disturbance immune flash EEPROM

Kuo-Ching Huang; Yean-Kuen Fang; Dun-Nian Yaung; Chung-Hui Chen; Y. P. Hsu; Shyh-Fann Ting; Yvonne Lin; Di-Son Kuo; Chung S. Wang; Mong-Song Liang

Abstract The program speed of a selected cell and the program disturbance of unselected cells sharing the common program-line in split-gate source-side injected flash memory has been investigated. It is found that the program disturbance becomes severe as the control gate length decreases. In this letter, we first propose a novel program technique by applying a negative bias to inhibited word-line to improve the trade-off between program speed and program disturbance. The experimental results indicate that the new program technique is a good candidate for future high-density, high-disturbance-immunity flash EEPROM memory applications.


Archive | 1997

Test structures for monitoring gate oxide defect densities and the plasma antenna effect

Hung-Der Su; Jian-Hsing Lee; Di-Son Kuo


Archive | 1998

Multi-level split- gate flash memory cell

Mong-Song Liang; Di-Son Kuo; Ching-Hsiang Hsu; Ruei-Ling Lin


Archive | 1998

Method of manufacture of vertical split gate flash memory device

Chrong Jung Lin; Shui-Hung Chen; Di-Son Kuo


Archive | 2005

Method to increase coupling ratio of source to floating gate in split-gate flash

Chia-Ta Hsieh; Yai-Fen Lin; Di-Son Kuo; Hung-Cheng Sung; Jack Yeh


Archive | 1996

Multi-level, split-gate, flash memory cell and method of manufacture thereof

Mong-Song Liang; Di-Son Kuo; Ching-Hsiang Hsu; Ruei-Ling Lin


Archive | 1998

Method of making embedded flash memory with salicide and sac structure

Jong Chen; Chrong Jung Lin; Hung-Der Su; Di-Son Kuo


Archive | 1998

Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices

Hung-Der Su; Jong Chen; Chrong-Jung Lin; Di-Son Kuo


Archive | 2000

Poly tip formation and self-align source process for split-gate flash cell

Hung-Cheng Sung; Di-Son Kuo; Chia-Ta Hsieh; Yai-Fen Lin

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