Jacqueline E. Rice

ESOP-based Toffoli Gate Cascade Generation

An ESOP-based Toffoli gate cascade synthesis algorithm is presented. The algorithm is capable of generating a cascade of reversible gates for logic functions with large numbers of qubits. The algorithm is fast as it uses a simple cost metric heuristic during a recursive divide-and-conquer function to determine NOT and Toffoli gate placement.

A new look at reversible memory elements

Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We present an analysis of a basic memory element, the RS-latch, and a number of possible implementations. We then go on to introduce four reversible flip-flop designs based on the reversible RS-latch implementation

An Introduction to Reversible Latches

Reversible logic has been suggested as one solution to the problem of power consumption in todays electronic devices. This paper addresses the issue of designing reversible latches and provides an overview and analysis of some proposed designs.

Ordering techniques for ESOP-based Toffoli cascade generation

This paper describes three techniques for ordering ESOP cubes prior to generation of a Toffoli gate generation. Two of these techniques are from earlier work, while the third is a new approach. The new approach applies rules to manipulate the cubes followed by a reordering process. Our experiments demonstrate that the new approach is much more effective than either of the two previous approaches. We apply template matching as a post-processing step, which results in even further reductions in the number of Toffoli gates.

An overview of fault models and testing approaches for reversible logic

Reversible logic has been proposed as one solution to the problem of ever increasing power consumption. Work in areas such as synthesis techniques in reversible logic is growing, as is work on testing approaches. Numerous fault models have been proposed, but many researchers are still utilising models proposed for traditional logic. We provide an overview of the various fault models and testing approaches for reversible logic, as well as highlighting important results and comparisons/connections between the various models.

Online Testable Approaches in Reversible Logic

We present an overview and analysis of existing work in the design of online testable reversible logic circuits, as well as propose new approaches for the design of such circuits. We explain how previously proposed approaches are unnecessarily high in overhead and in many cases do not provide adequate fault coverage. Proofs of the correctness of our approaches are provided, and discussions of the advantages and disadvantages of each design approach are given. Experimental results comparing our approaches to existing work are presented as well. Both approaches that we propose have better fault coverage and significantly lower overheads than previous approaches.

A simple approach for designing online testable reversible circuits

This paper presents a simple technique to convert an ESOP-based reversible circuit into an online testable circuit. The technique does not require redesigning the whole circuit for integrating the testability feature, and no new garbage outputs are produced other than the garbage outputs needed for the ESOP-circuit. With a little extra hardware cost, the resultant circuit can detect online any single-bit errors. Experimental results show that the proposed technique can achieve an improvement of up to 58% in quantum cost and 99% in garbage outputs in average, compared to the previous work.

A Lightweight Architecture for Secure Two-Party Mobile Payment

The evolution of wireless networks and mobile devices has resulted in increased concerns about performance and security of mobile payment systems. In this paper we propose SA2pMP, a lightweight secured architecture for two-party mobile payments. SA2pMP employs a lightweightcryptography scheme that combines public key and symmetric key cryptography systems (ECDSA and AES), as well as a multi-factor authentication mechanism. These are coupled with a transaction log strategy to satisfy the properties of confidentiality, authentication, integrity and nonrepudiation. We simulate SA2pMP in a context of money transfer banking transaction, on three different emulators:Sun Java Wireless Toolkit 2.5.2 for CLDC emulator, Sony Ericsson SDK 2.5.0.3 Z800 emulator, and Nokia S60 3rd Edition emulator. We also compare SA2pMP to some existing mobile payment platforms. The result of simulation and comparison proves that SA2pMP is a lightweight secured mechanism that is feasible and suitable for two-party mobile payment transactions, e.g. mobile banking, over Java ME enabled, resource-limited mobile devices.

Antisymmetries in the realization of Boolean functions

New symmetries of degree two are introduced, along with spectral techniques for identifying these symmetries. Some applications of these symmetries are discussed, in particular their application to the construction of binary decision diagrams and the implementation of Boolean functions.

Online Fault Detection in Reversible Logic

A new approach for online fault detection in Boolean reversible circuits is described. Previous work had described this approach for circuits generated by the basic ESOP-based logic synthesis, and in this work we extend the approach for any type of Toffoli networks. An online testable circuit is created by modifying an existing cascade of Toffoli gates in a simple process that involves changing the existing Toffoli gates as well as the addition of one line and 2p gates, where p is the number of lines in the original circuit.