Micaela Serra

The analysis of one-dimensional linear cellular automata and their aliasing properties

It is shown how to construct a general linear hybrid cellular automaton (CA) such that it has a maximum length cycle, and how the aliasing properties of such automata compare with linear feedback shift registers (LFSRs) when used as signature analyzers. The construction is accomplished by formally demonstrating the isomorphism which binds this kind of CA to the LFSRs. Consequently, these CAs can be analyzed as linear machines. Linear algebraic techniques are then applied appropriately for the transformations, and a useful search algorithm is developed which, given an irreducible characteristic polynomial, finds a corresponding linear hybrid automaton. Such CAs are tabulated for all irreducible and primitive polynomials up to degree 16, plus a selection of others of higher degree. The behavior of a linear hybrid CA and that of its corresponding LFSR are similar-that is, they have the same cycle structure and only relabel the states. The aliasing properties, when they are used as signature analyzers, remain unchanged. >

Fast Algorithms to Generate Necklaces, Unlabeled Necklaces, and Irreducible Polynomials over GF(2)

Many applications call for exhaustive lists of strings subject to various constraints, such as inequivalence under group actions. A k-ary necklace is an equivalence class of k-ary strings under rotation (the cyclic group). A k-ary unlabeled necklace is an equivalence class of k-ary strings under rotation and permutation of alphabet symbols. We present new, fast, simple, recursive algorithms for generating (i.e., listing) all necklaces and binary unlabeled necklaces. These algorithms have optimal running times in the sense that their running times are proportional to the number of necklaces produced. The algorithm for generating necklaces can be used as the basis for efficiently generating many other equivalence classes of strings under rotation and has been applied to generating bracelets, fixed density necklaces, and chord diagrams. As another application, we describe the implementation of a fast algorithm for listing all degree n irreducible and primitive polynomials over GF(2).

2-by-n hybrid cellular automata with regular configuration: theory and application

This paper introduces a new class of two-dimensional linear cellular automata and derives a number of their properties. A recursive relation is proved which enables the characteristic polynomial to be efficiently calculated, and minimal cost, maximal length generators of this type are listed for sizes up to 500. A theoretical analysis of the two vector transition properties of the cellular automata is given and it is shown that, for testing sequential faults over a set of standard benchmarks, the two-dimensional cellular automata perform, on average, better than one-dimensional linear hybrid cellular automata, and much better than linear finite shift registers.

The generation of rimitive olynomials in GF(q) with independent roots and their applications for ower residue codes, VLSI testing and finite field multipliers using normal basis

The interest of this research is in finding rimitive olynomials with linearly independent roots over the Galois field of q elements, GF(q). Existing methods are sufficient only to generate a single olynomial. Here they need to be enumerated in order to apply further selections in view of the applications. The olynomials are generated through a search algorithm extensively runed using some known results and newly derived corollaries. Tables of these olynomials are given over fields up to GF(19) for the first time. The common background for the applications is in forming a normal basis from the linearly independent roots. Three applications are discussed, each including new results: the transformation of ower residue codes to quasi-cyclic codes; the VLSI implementation of multiplication and inverse operations over Galois fields and the acceleration of BCH error correcting code decoding; and the superior aliasing robabilities for the digital testing of integrated circuits

Hardware/software co-design of a Java virtual machine

We discuss the initial results of research into the development of a hardware/software co-design of the Java virtual machine. The design considers a complete Java virtual machine with full functionality expected to run with the same capabilities as a fully software Java virtual machine. We address issues such as why a partial hardware implementation is suitable, the challenges in realizing this goal, propose an initial partitioning of the virtual machine between hardware and software, discuss the desired hardware requirements and discuss some details of the hardware and software design.

Testing Programmable Logic Arrays by Sum of Syndromes

Syndrome testing is a simple and effective fault detection technique applicable to many general circuits. It is particularly useful in two-level circuits, such as programmable logic arrays (PLAs). For a multiple-output network, like PLAs, existing methods test the individual syndromes for each function, where a fault should be detectable in at least one output. This paper shows that the weighted sum of syndromes of all the outputs covers all single stuck-at-faults, bridging faults, and cross-point faults. Primary input faults are also covered except in one special case which requires some preventive design for testability. This results in the use of one test to cover all single faults.

Hardware architecture for Java in a hardware/software co-design of the virtual machine

This paper discusses the hardware architecture used in the hw/sw co-design of a Java virtual machine. The paper briefly outlines the partitioning of instructions and support for the virtual machine. Discussion concerning the hardware architecture follows focusing on the special requirements that must be considered for the target environment. A comparison is performed between this design and that of picoJava, a stand-alone processor for Java. The paper concludes with benchmark results for this architecture compared with software execution.

An object-oriented layered approach to interfaces for hardware/software codesign of embedded systems

The Canadian Microelectronics Corporation has developed and distributed a rapid prototyping board (RPB) to facilitate research in hardware/software (HW/SW) codesign, case studies, applications and prototyping of projects in embedded systems. This research develops a series of layers between hardware and software, exploiting the dynamically reconfigurable hardware of the RPB and creating the connection to host processes and software layers in general, both on the board itself, and between a HW/SW system downloaded to the board and its host workstation. We describe a new approach which uses object oriented technology as the basis for the system design methodology, the specifications and the implementation, providing a flexible and dynamic foundation, lending itself to further expansion and research in HW/SW codesign.

Using FPGAs to solve the Hamiltonian cycle problem

The Hamiltonian Cycle (HC) problem is an important graph problem with many applications. The general backtracking algorithm normally used for random graphs often takes far too long in software. With the development of field-programmable gate arrays (FPGAs), FPGA-based reconfigurable computing offers promising choices for acceleration. This research exploits the idea of an instance-specific approach and proposes a system design based on a reconfigurable hardware implementation for solving the HC problems. In our implementation, only one FPGA is used, on an internal PCI-based board. The experimental results show that the reconfigurable hardware approach yields significant runtime speedups over the conventional approach, although the clock rate of the FPGA hardware is much slower than that of the workstation running the software solver.

MERGING CONCURRENT CHECKING AND OFF-LINE BIST

We present a new testing scheme which merges concurrent checking and 08-line BIST using signature analysis. The hardware resources are shared, with minimal overhead. It supports IEEE Boundary-scan standard and is applicable to general circuitry.