Jae-hoon Joo

Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM

Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using the BLC scheme. BLC scheme also improves the low VCC margin by 0.3 V and the RAS to CAS delay time (tRCD) by 1.5 ns. Differential current evaluation for the E-fuse implementation shows polysilicon fuse fail rate <10/sup -12/.

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method

Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposed methodology consists of a defect-based wafer burn-in (DB-WBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.