Jae Wook Jeon

FPGA Design and Implementation of a Real-Time Stereo Vision System

Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies.

Introduction for Freshmen to Embedded Systems Using LEGO Mindstorms

The purpose of the course presented here is to introduce freshmen to embedded systems using LEGO Mindstorms, under an ANSI-C programming environment. The students build their own LEGO robots, make programs for them using ANSI-C, and operate them. By creating these LEGO robots, the students become more motivated, learning the basic concepts of embedded systems and how these concepts can be applied to real world problems.

An FPGA-Based Multiple-Axis Motion Control Chip

This paper presents the design and implementation of a multiple-axis motion control chip using a field-programmable gate array (FPGA). This multiple-axis motion control chip is designed to control a multiple-axis motion system such as a robotic arm manipulator or a computer numerical control machine. The proposed motion control chip has many functions. These include velocity profile generation, interpolation calculation, inverse kinematics calculation, proportional-integral-derivative control, feedback count, pulse integration, data conversion, clock generation, and external interfacing. These functions are designed using the VHSIC hardware description language and implemented on an FPGA according to the electronic design automation design methodology. This allows for a highly sampled, accurate, flexible, compact, low-power, and low-cost motion control system. The detailed design of the proposed motion control chip is presented. A multiple-axis motion control system using this chip is implemented, and its performance is measured. The multiple-axis motion control system is implemented on a platform consisting of a chip-based multiple-axis motion controller, analog ac servo drivers, a selective compliant assembly robot arm robot, and a host personal computer.

Evaluating performance of Android platform using native C for embedded systems

The Android platform used for mobile devices can be applied to embedded systems, such as robot control systems. Developers should create applications by using Java language provided by Android SDK for embedded systems operated via Android platforms. However, in many existing embedded systems, developers have written applications for controlling the system by using C language. Android NDK makes it possible for developers to easily reuse such legacy code written in C/C++ languages. In this paper, we show the difference in terms of performance between an Android application using native code library from C source and an Android application using the same algorithm written in Java language only. We conducted an experiment on five parts: JNI communication delay, integer calculation, floating-point calculation, memory access algorithm, and heap memory allocation algorithm. This paper presents a guideline for an effective way to use native code libraries in Android applications.

Domain Transformation-Based Efficient Cost Aggregation for Local Stereo Matching

Binocular stereo matching is one of the most important algorithms in the field of computer vision. Adaptive support-weight approaches, the current state-of-the-art local methods, produce results comparable to those generated by global methods. However, excessive time consumption is the main problem of these algorithms since the computational complexity is proportionally related to the support window size. In this paper, we present a novel cost aggregation method inspired by domain transformation, a recently proposed dimensionality reduction technique. This transformation enables the aggregation of 2-D cost data to be performed using a sequence of 1-D filters, which lowers computation and memory costs compared to conventional 2-D filters. Experiments show that the proposed method outperforms the state-of-the-art local methods in terms of computational performance, since its computational complexity is independent of the input parameters. Furthermore, according to the experimental results with the Middlebury dataset and real-world images, our algorithm is currently one of the most accurate and efficient local algorithms.

A Real-Time Object Tracking System Using a Particle Filter

Particle filters have attracted much attention due to their robust tracking performance in cluttered environments. Particle filters maintain multiple hypotheses simultaneously and use a probabilistic motion model to predict the position of the moving object, and this constitutes a bottleneck to the use of particle filtering in real-time systems due to the expensive computations required. In order to track moving objects in real-time without delay and loss of image sequences, a particle filter algorithm specifically designed for a circuit and the circuit of the object tracking algorithm using the particle filter are proposed. This circuit is designed by VHDL (VHSIC hardware description language), and implemented in an FPGA (field programmable gate array). All of the functions of the proposed particle filter used to track moving objects are implemented in the FPGA. The object tracking system employing this circuit is implemented and then its performance is measured

Neural-Network-Based Low-Speed-Damping Controller for Stepper Motor With an FPGA

We present a low-speed-damping controller for a stepper motor using artificial neural networks (ANNs). This controller is designed to remove nonlinear disturbance at low speeds. The proposed controller improves the stepper motor performance at less than the resonance speed of the stepper motor system. Due to its ability to learn, the proposed controller can adapt to different resonant speed ranges without any identification process for system parameters. Conversely, we also introduce the implementation of an ANN-based controller, online backpropagation learning, and a microstep driver on a single field-programmable gate array. An implementation and experimental results are conducted to verify the feasibility and the effectiveness of the proposed controller.

Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA

This paper presents design and implementation of a pipelined datapath for real-time face detection using cascades of boosted classifiers. We propose following methods: symmetric image downscaling, classifier sharing, and cascade merging, to achieve the desired processing speed and area efficiency. First, an image pyramid with 16 levels is generated from the input image to simultaneously detect faces with different scales. The downscaled images are then transferred to the first stage of the cascade that is shared between the corresponding image pairs based on the pixel validity of the symmetric image pyramid. The last method exploits the different hit ratios of the cascade stages. We use a tree-structured cascade of classifiers since most of the nonface elements are eliminated during the early stages of the classifier. The use of a synthesis tool confirms that the proposed design reduces resource utilization by one-eighth without accuracy loss, compared to the fully parallelized implementation of the same algorithm. We implemented the proposed hardware architecture on a Xilinx Virtex-5 LX330 FPGA. The indicative throughput is 307 frames/s irrespective of the number of faces in the scene for standard VGA (640 × 480) images with an operating frequency of 125.59 MHz. We may ensure that face detection results are generated at each clock cycle after the initial pipeline delay, using this fully pipelined datapath for tree-structured cascade classifiers.

An Efficient Approach to Correct the Signals and Generate High-Resolution Quadrature Pulses for Magnetic Encoders

A magnetic encoder (ME) is a kind of sinusoidal encoder using magnetic effects that is currently utilized in many industrial control systems because it has many advantageous characteristics: low cost, simple structure, works in harsh environments, high reliability, and so on. The signals generated by an ME are always disturbed by noises; therefore, these signals are not ideal. The challenge is to achieve the highest resolution and to get the maximum operating speed as well as to use the most cost-effective hardware. To solve this problem, this paper humbly proposes an effective approach, which contains two parts: The main part is “compensating the noisy signals of MEs” by applying a new proposed method called the advanced adaptive digital phase-locked loop (AADPLL), while the second is a pulse interpolator which generates high-resolution quadrature pulses. The AADPLL algorithm provides a robust filtering characteristic to eliminate the noises and improve the accuracy of the MEs input signals. It also takes advantage of tracking high-speed input signals without time lag, unlike the traditional filters. Additionally, the computation burden is significantly reduced in this algorithm to allow it to be easily implemented in a low-cost processor. The pulse interpolator is based on an existing idea that extracts high-order sinusoids from the original ME signals. However, a new scheme is presented to achieve higher resolution per period with smaller noises affecting the output pulses. Both parts are mainly implemented in a unique hardware platform using a low-cost digital signal processor, such as the TMS320F2812, combined with a small-size field-programmable gate array. This method has already been applied to control a linear motor without using an expensive optical linear encoder. Practical results are provided to demonstrate the effectiveness of the proposed method.

Remote robot control system based on DTMF of mobile phone

In the age of ubiquitous systems it is important to be able to control robots everywhere. Although many methods to remotely control robots have been devised, the methods have the problems such as the need for special devices or software to control the robots. This paper suggests a method for robotic control using the DTMF tone generated when the user pushes mobile phone keypad buttons o when connected with a remote mobile robot.