Jaehwan Jung

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory

To improve the reliability of MLC NAND flash memory, this paper presents an energy-efficient high-throughput architecture for decoding concatenated-BCH (CBCH) codes. As the data read from the flash memory is hard-decided in practical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capability and energy efficiency. In the proposed CBCH decoding, the number of on-chip memory accesses consuming much energy is minimized by computing and updating syndromes two-dimensionally. To achieve an area-efficient hardware realization, row and column decoders are unified into one decoder and some syndromes are computed when they are needed. In addition, the decoding throughput is enhanced remarkably by skipping redundant decoding processes. Based on the proposed CBCH decoding architecture, a prototype chip is implemented in a 65-nm CMOS process to decode the (70528, 65536) CBCH code. The proposed decoder provides a decoding throughput of 17.7 Gb/s and an energy efficiency of 2.74 pJ/bit, being vastly superior to the state-of-the-art architectures.

Area-Efficient Multimode Encoding Architecture for Long BCH Codes

This brief presents a new area-efficient multimode encoder for long Bose-Chaudhuri-Hocquenghen codes. In the proposed multimode encoding architecture, several short linear-feedback shift registers (LFSRs) are cascaded in series to achieve the same functionality that a long LFSR has, and the output of a short LFSR is fed back to the input side to support multimode encoding. Whereas previous multimode architectures necessitate huge overhead due to preprocessing and postprocessing, the proposed architecture completely eliminates the overhead by exploiting an efficient transformation. Without sacrificing the latency, the proposed architecture reduces hardware complexity by up to 97.2% and 49.1% compared with the previous Chinese-remainder-theorem-based and weighted-summation-based multimode architectures, respectively.

Low-Complexity Tree Architecture for Finding the First Two Minima

This brief presents an area-efficient tree architecture for finding the first two minima as well as the index of the first minimum, which is essential in the design of a low-density parity-check decoder based on the min-sum algorithm. The proposed architecture reduces the number of comparators by reusing the intermediate comparison results computed for the first minimum in order to collect the candidates of the second minimum. As a result, the proposed tree architecture improves the area-time complexity remarkably.

Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems

This letter presents a new multi-bit flipping decoding algorithm for low-density parity-check codes, which can enhance hard-information-based decoding performance for NAND storage systems. Since the conventional enhancement techniques developed for bit-flipping decoding require soft information, the long latency taken to generate the soft information, makes it hard to apply them to practical NAND storage systems. The proposed algorithm requires only hard information and achieves the better performance than previous hard-information-based algorithms. The proposed method flips multiple bits in each iteration, but the maximum number of bits to be flipped in an iteration is restricted to prevent overcorrection. To relax the hardware complexity of sorting, in addition, an efficient approximation method is proposed, reducing the hardware complexity of a 512-input sorter by 48.3% without degrading the performance noticeably.

Unidirectional ring ethernet for low-complexity in-vehicle control network

This paper proposes a low-complexity automotive control network based on Ethernet. Modern vehicles suffer from heavy wiring harness caused by multiple control networks such as controller area network (CAN) and FlexRay. The proposed network connects electronic control units (ECUs) by a unidirectional ring network, reducing the wiring cost significantly. The performance of the proposed network is evaluated using the OMNET++ simulation tool with adopting realistic models of automotive control packets in order to investigate two metrics, the maximum number of ECUs and the minimum interval of packet transmission. As a result, the proposed network is proven to be a promising method that can connect more than a hundred of ECUs with the simple ring topology. Furthermore, valuable guidelines effective in deciding the specification of the proposed network are derived.

Efficient Parallel Architecture for Linear Feedback Shift Registers

This brief presents a new parallel architecture for linear feedback shift registers (LFSRs), which can be used to achieve high-throughput Bose-Chaudhuri-Hocquenghem or cyclic redundancy check encoders for storage and communication systems. While previous parallel LFSR architectures have computed values by using the past input messages and the register outputs, the proposed parallel architecture based on the transposed serial LFSR calculates the output by using only the past feedback values. As a result, the proposed architecture reduces the area-time product by up to 59% compared with the recent architecture.

Area-Efficient Approach for Generating Quantized Gaussian Noise

This paper presents an efficient method to generate quantized Gaussian noise. The proposed method is derived based on the fact that any signal received at a digital system should be quantized to several bits. On the contrary to the previous works that have focused on the precision of noise, the quantization process is taken into account in generating noise samples. As a result, the resultant bit-width of noise is significantly reduced and the computation complexity of generating Gaussian noise is also reduced by simplifying the interpolation process. The proposed architecture based on the inversion method is implemented on field-programmable gate array (FPGA) devices. Compared to the previous architecture based on the conventional inversion method, the proposed approach improves the throughput per slice by 460% while maintaining the statistical properties of Gaussian noise.