Injae Yoo

6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers

Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1-2]. However, the performance of SSD is in general determined by the throughput of the ECC blocks necessary to overcome the high error-rate [3]. The binary BCH code is widely used for the SSD due to its powerful error-correction capability. As it is hard to achieve high-throughput strong BCH decoders [4-5], multiple BCH decoders are typically on a high-performance SSD controller, leading to a significant increase of hardware complexity. This paper presents an efficient BCH encoder/decoder architecture achieving a decoding throughput of 6Gb/s. The overall architecture shown in Fig. 25.3.1 includes a single BCH decoder and a multi-threaded BCH encoder. The single BCH encoder is responsible for all the channels and services a channel at a time in a round-robin manner.

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm2.

Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns

In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

This paper proposes a novel decoding algorithm to enhance the throughput of turbo decoding in LTE-Advanced systems and its hardware realization. The proposed method completely removes the undesired phase-switching latency by partially overlapping in-ordered and interleaved decoding phases, and as a result, achieves a significant increase of decoding throughput. Moreover, the algorithm does not degrade error-correcting performance for high-rate codes which are essential to achieve the maximum data rate of LTE-Advanced systems. The proposed method called tail-overlapped decoding can be easily applied to the conventional parallel decoding architecture designed for standardized communication systems. In addition, a new structure for the extrinsic information memory is proposed to eliminate memory contentions. A 3GPP LTE-Advanced turbo decoder supporting both decoding methods is implemented in 0.13 μm CMOS technology to show the effectiveness of the proposed algorithm. The decoder exhibits a decoding rate greater than 1Gbps with six iterations, meeting the peak data rate of the LTE-Advanced standard with much less hardware complexity than those of the previous works.

A search-less DEC BCH decoder for low-complexity fault-tolerant systems

This paper proposes a new decoding algorithm and its decoder architecture to completely remove the parallel Chien search in double error correcting (DEC) BCH decoders. The proposed algorithm called search-less decoding utilizes a quadratic formula to efficiently compute the roots of an error-location polynomial in the finite field. Since the parallel Chien search block dominates the overall complexity of a conventional DEC BCH decoder, the proposed algorithm is effective in mitigating the hardware complexity. Furthermore, a search-less (44, 32, 2) BCH decoder architecture is proposed for fault-tolerant embedded systems. Compared to the conventional decoder associated with 16-parallel Chien search, the proposed decoder decreases the hardware complexity by 51% without sacrificing the decoding throughput.

Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks

This brief proposes a low-power low-density parity check convolutional code (LDPC-CC) decoder that is fully compatible with the IEEE 1901 standard. The proposed architecture merges multiple memory banks into one to make it consume much less power than the conventional architecture. Memory operations conducted by all the unit processors are synchronized in the proposed decoder to merge the memory and avoid any possible data hazard. The data hazard happens when a unit processor tries to read a log-likelihood ratio before a different processor updates it, degrading the error-correcting performance. Memory-access patterns appearing in a memory-based LDPC-CC decoder are formulated to determine the size of a sliding window adequate for decoding. Experimental results show that the decoding architecture employing the merged memory and the proper window size reduces the power consumption by up to 40% compared to the conventional architecture that employs multiple memory banks.

Unidirectional ring ethernet for low-complexity in-vehicle control network

This paper proposes a low-complexity automotive control network based on Ethernet. Modern vehicles suffer from heavy wiring harness caused by multiple control networks such as controller area network (CAN) and FlexRay. The proposed network connects electronic control units (ECUs) by a unidirectional ring network, reducing the wiring cost significantly. The performance of the proposed network is evaluated using the OMNET++ simulation tool with adopting realistic models of automotive control packets in order to investigate two metrics, the maximum number of ECUs and the minimum interval of packet transmission. As a result, the proposed network is proven to be a promising method that can connect more than a hundred of ECUs with the simple ring topology. Furthermore, valuable guidelines effective in deciding the specification of the proposed network are derived.

Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes

To provide near-optimal error-correcting performance for multi-rate turbo codes and minimize the size of additional memory, a new decoding method is proposed in this paper. The proposed decoding is based on two methods: hybrid sliding window and dynamic metric encoding. The new window scheme combines dummy metric calculation and border metric storing methods to halve the border metric memory and improve the error-correcting performance for multi-rate codes. The dynamic encoding of metrics also significantly reduces the border metric memory without degrading the performance. Employing the two proposed methods reduces the conventional border metric memory by 83%. In addition, the superb error-correcting performance of the proposed method is verified for various code rates by conducting intensive simulations for 3GPP LTE codes.

Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture

An efficient decoding architecture for triple-error-correcting BCH codes is proposed by utilizing a lookup table (LUT) that stores the roots of the error locator polynomial instead of using the Chien search. Two roots of the polynomial equation are precomputed and stored in the LUT in order to relax the hardware complexity. To relax the complexity further, a new method to compress the LUT is additionally proposed. While a large portion of the LUT is filled with unnecessary information in the previous designs, this brief eliminates the redundant information by investigating an algebraic property of the equation. For BCH codes over GF(210), the LUT size is reduced to 18% of the previous work. As a result, the proposed decoding architecture reduces the decoding latency by 38% and the equivalent gate count by up to 40% compared to the previous work, achieving a fast low-complexity triple-error-correcting BCH decoder.

Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders

In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%.