Jaeil Lim

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability

Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in todays and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues.

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations

Process variations yield the asymmetry on core performance in many-core processors. Adaptive voltage scaling can hide the variations, but that results in the different thermal characteristics of cores. By using the thermal characteristics, the efficiency of energy optimization and temperature management can be improved. Experiments showed that the proposed dynamic voltage frequency scaling consumes up to 25.2% less energy than the existing thermal management technique while remaining the ratio of peak temperature violations under 1%.

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability

The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.

Process variation-aware floorplanning for 3D many-core processors

Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.

Thermal Aware Test Scheduling for NTV Circuit

Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss.

Reconfigurable scan architecture for Test Power and Data Volume Reduction

With exponential development in the semiconductor technology in recent years, the magnitudes of test power consumption and test data volumes have increased significantly. This has resulted in over-testing because of IR drops. This paper proposes a reconfigurable scan architecture to overcome these challenges. The proposed architecture increases the flexibility of the scan partitioning technique to maximize the reduction in the switching activity, and it uses the scan segment skip technique to reduce the data volume. The results show that our method is able to achieve significant reductions in the total test power and data volumes compared with previous methods.

A novel X-filling method for capture power reduction

This paper proposes a X-filling method that reduces capture power during scan-based testing. The proposed method classifies scan cells for dividing the scan cells into some groups. Then, based on the divided groups, X-bits are filled simultaneously to reduce the computation time. Since the proposed method uses a novel grouping algorithm and fills X-bits based on groups, the proposed method reduces switching activity and computation time when compared with conventional X-filling methods. The simulation results show that the proposed method reduces the switching activity up to 70% and the number of simulations for the X-filling up to 52% compared with that of conventional X-filling methods.

Process variation-aware bridge fault analysis

Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.

Recovery-enhancing task scheduling for multicore processors under NBTI impact

Task scheduling for multicore processors typically has aimed at higher throughput and lower power consumption, but the lifetime reliability may be harmed if negative bias temperature instability is not considered together. In this letter, a task scheduling which extends lifetime is proposed. Cores are given the chance to recover as long as performance is not degraded. The degradation simulator shows that the proposed scheduling improves the lifetime of a multicore processor by up to 36% over the existing task scheduling.

Dynamic thermal management for 3D multicore processors under process variations

Stacking core layers is emerging as an alternative for future high performance computing, but thermal problems have to be tackled first. When adaptive voltage scaling is adopted to hide the growing variation in the performance of cores, as a result, heat generation of each core varies. By exploiting the static thermal characteristics, the efficiency of dynamic thermal management can be improved. The proposed thermal management reduces the energy consumption by up to 30.02% compared with existing techniques, while keeping the ratio of temperature violations around 1%.