Jaewon Han

Impact of Surface Treatment on Resist Reflow Process

Resist reflow techniques have widely been adopted for lithography in resolution limited region. During the reflow process, resist patterns are heated over its glass temperature through number of temperature steps. Early works have focused how the temperature steps during heat-up process can be effectively controlled for critical dimension (CD) and the pattern profile after reflow. However, for a specific application that needs moderate CD and profile change, adjusting heat-up parameters would not be sufficient to achieve good CD and profile control and additional relevant parameters should be accounted. In this paper, we count surface treatment condition on reflow process as an additional control parameter. We measured CDs with varying surface treatment parameters of substrate on square arrays of resist islands with 300 nm island-to-island gap space. We found that the amount of after develop CD to after reflow CD bias decreases as contact angles of substrates increases. In conclusion, we prove the resist reflow CD can be controlled precisely by adjusting the substrate coverage of hydroxyl groups during adhesion treatments in addition to the temperatures for the resist reflow process.

90nm node contact hole patterning through applying model based OPC in KrF lithography

As semiconductor technologies move toward 90nm generation and below, contact hole is one of the most challenging features to print in the semiconductor manufacturing process. There are two principal difficulties in order to define small contact hole pattern on wafer. One is insufficient process margin besides poor resolution compared with line & space pattern. The other is that contact hole should be made through pitches and sometimes random contact hole pattern should be fabricated. Therefore advanced ArF lithography scanner should be used for small contact hole printing with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC(Optical Proximity Correction), PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), mask biasing and thermal flow. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest the method of contact holes patterning by using KrF lithography tool in 90nm sFlash(stand alone Flash)devices. For patterning of contact hole, we apply RETs which combine OAI and Model based OPC. Additionally, in this paper we present the result of hole pattern images which operate ArF lithography equipment. Also, this study describes comparison of two wafer images that ArF lithography process which is used mask biasing and Rule based OPC, KrF lithography process which is applied hybrid OPC.

Copper Hillock Induced Copper Diffusion and Corrosion Behavior in a Dual Damascene Process

A copper hillock induced interconnect failure mechanism is presented. The copper hillock is frequently generated during a copper dual damascene process and hillock formation is found to degrade the interconnect integrity by affecting the following process steps. The copper hillock appears to damage the SiN capping layer and results in copper corrosion during via etch. The corrosion generates copper particles inside via holes and the defects are found to make the following metal depositions incomplete during via formation. Based on the observations, a copper hillock induced defect model is proposed and a new copper process is suggested to reduce copper hillocks.

Improvement of KrF contact layer by inverse lithography technology with assist feature

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

Patterning of 90nm node flash contact hole with assist feature using KrF

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

Effective methodology to make DFM guide line

Design For Manufacturing (DFM) has become an important focusing part in the semiconductor industry as the feature size on the chip goes down below the 0.13um technology. Lots of DFM related ideas have been come up, tried, and adopted for wider process window and higher device performance. As the minimum features are getting shrunk, the design rules also become more complicated, but still not good enough to describe the certain pattern that imposes narrow process window or even failure of device. Thus, these process hot spot patterns become to identify, correct, or remove at the design step. One of the efforts is to support a DFM guide line to the designer or add to conventional DRC rules. However it is very difficult to make DFM guideline because we detect the hot spot pattern and confirm if these patterns is real hot spot or not. In this study, we developed effective methodology how to make DFM guide line. Firstly we use the s oftware, called nanoscope to detect hot spots on post OPC layouts and then make this detected hot spot patter n to test patterns that it can check electrical performance and then we compared with electrical performance a ccording to split condition. It is confirmed this method is very effective to make DFM guide line below the 0. 13um technology.

Advanced mask technique to improve bit line CD uniformity of 90 nm node flash memory in low-k1 lithography

As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer. One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC, PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to get more stable properties then before applying this technique.

Investigation of mechanism of pattern deformation on TiN substrate and O2 plasma effect without BARC

The pattern deformation such as photoresist lifting after lithography due to not enough photoresist adhesion to substrate is become critical issue when aspect ratio is much higher than what photoresist adhesion can support. This aspect ratio is getting higher when our design rule of device requests smaller feature size in lithography process. The BARC (Bottom Antireflective Coating), which advanced lithography is using, is very good layer to improve adhesion of photoresist since they are same kind of chemical. However, BARC needs extra etching process before main etching which is step to remove substrate. Sometimes, this BARC etching step generated defects which makes yield loss. Especially, lithography step for metallization with aluminum likes without BARC process to be free from those defect. We think that adhesion of photoresist on metal substrate such as aluminum or TiN is very important to develop lithography process without BARC. The adhesion change between photoresist and metal substrate will be changed as function of how we apply pretreatments for metal substrate. The typical pretreatments before patterning are dry ash, wet cleaning and HMDS treatment. In this paper, we study that adhesion changes as function of pretreatments and their mechanism. To understand the interaction between photoresist and substrate, we analyze surface change of wafers which prepared with several different experimental conditions using XPS (X-ray photoelectron spectroscopy) and Dynamic Contact Angle Analyzer. The results will explain how photoresist adhesion may be changed with different pretreatment conditions and how we can optimize process condition to improve photoresist adhesion without BARC.

Impact of assistance feature to pattern profile for isolated feature in sub-65 nm node

Sub-resolution assistance feature (SRAF) has become one of popular resolution enhancement technique because it is the most easily applicable technique that can be adopted for sub-65 nm node technology. The SRAF can be realized, for example, by locating lines having width below resolution limit around isolated feature. With the SRAF, intensity profile of the isolated feature will be modified to dense-like one and, as a result, focus response of the isolated feature can be improved up to dense feature level. Previous works on SRAF have focused mainly on the critical dimension (CD) margin window. However, CD margin window is not sufficient to evaluate optimum SRAF configuration because process margin degradation due to irregular pattern profile such as line edge roughness (LER) would become more prominent as technology node goes beyond sub-65nm node. Therefore, appropriate methodology to optimize SRAF configuration both for CD margin window and pattern profile is indispensable for those applications. In this paper, we focus on the impact of SRAF configuration to pattern profile as well as CD margin window. The SRAF configuration was adjusted by varying assistance feature to main feature distance and pitch of the assistance features at mask level. Pattern profile was investigated by measuring LER with varying assistance feature parameters quantitatively. From the results, we prove the impact of SRAF configuration both on pattern profile and CD margin window. We also show that the experimental data can easily be predicted by calibrating aerial image simulation results to measured LER. As a conclusion, we suggest methodology to set up optimum SRAF configuration with regard to both CD margin window and pattern profile.

OPC modeling setup with considering flare effect

Flare is unwanted light arriving at the wafer and light causing negative impact on pattern formation. It is caused by scattered light from lens surfaces, problem on lens design, or problem on lens manufacture. The impact of flare varies printed line widths or drops CD uniformity accuracy in full chip. And, It is an added incoherent background intensity that will degrade OPC(Optical Proximity Correction) accuracy[1]. In this paper, we discussed CD variation, MEEF (Mask Error Enhancement Factor) and OPC accuracy by the flare effects. Flare is bound up with local pattern density. Local pattern density influences background intensity by flare or stray light. So we studied CD variation, MEEF, OPC modeling data with local pattern density by several experiment. Also, in this study, we will discuss test pattern drawing for OPC modeling data, analyze CD difference between OPC test pattern with considering flare effect and test pattern with regardless flare effect and MEEF value by flare effect. MEEF is main factor that influences lithography process margin. This paper will show test pattern optimization in OPC modeling.