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Dive into the research topics where Jai Narayan Tripathi is active.

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Featured researches published by Jai Narayan Tripathi.


international symposium on quality electronic design | 2012

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization

Jai Narayan Tripathi; Raj Kumar Nagpal; Nitin Kumar Chhabra; Rakesh Malik; Jayanta Mukherjee

To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found.


2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE) | 2014

A comparative analysis of jitter estimation techniques

Vijender Kumar Sharma; Jai Narayan Tripathi; Rajkumar Nagpal; Sujay Deb; Rakesh Malik

With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.


world congress on information and communication technologies | 2011

Optimization of Analog RF Circuit parameters using randomness in particle swarm optimization

Sudheer Kamisetty; Jyoti Garg; Jai Narayan Tripathi; Jayanta Mukherjee

This paper presents stochastic convergence analysis of particle swarm optimization algorithm involving randomness and applying the results to the Analog RF Circuits to optimize the circuit parameters. In every iteration, each particle position is represented as vector and the standard particle swarm algorithm determined by positive real tipple {w,c1,c2}. Comparisons for convergence are presented with respect to fixed tipple {w,c1,c2} and random tipple {w,c1,c2}. Various results show that the randomness in defining new position to particle leads to better convergence property. Also, exploration and exploitation trade off are discussed with examples. It is demonstrated that each particle undergoes both exploration and exploitation in convergence process; if the randomness in the particle generation is considered. The parameters considered for RF circuit are cutoff frequency, Phase Noise and Signal to Noise Ratio (SNR). Results are compared between both fixed values and random values of parameters in convergence analysis of PSO.


international symposium on quality electronic design | 2013

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization

Jai Narayan Tripathi; Raj Kumar Nagpal; Nitin Kumar Chhabra; Rakesh Malik; Jayanta Mukherjee; Prakash R. Apte

Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel and accurate methodology is presented which can be used for any high speed Power delivery Network.


electrical performance of electronic packaging | 2013

A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits

Jai Narayan Tripathi; Jayanta Mukherjee; Prakash R. Apte; Raj Kumar Nagpal; Nitin Kumar Chhabra; Rakesh Malik

A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier published structures. Suppression of resonant cavity modes of power plane by EBG structure is also shown. The adoption of EBG structure in power deliver network is recommended to reduce the high frequency noise coupling between neighboring devices. These structures further help in better EMI/EMC compliance of the product by attenuating the propagation of high frequency noise between devices. The EBG structure usage can be on board, package or at die level.


networked embedded systems for enterprise applications | 2010

Robust optimization of serial link system for signal integrity and power integrity

Jai Narayan Tripathi; Raj Kumar Nagpal; Rakesh Malik

Signal Integrity (SI) and Power Integrity (PI) are the most critical issues for higher operational speeds in semiconductor industry. This work identifies and optimizes the parameters of board, package and termination environment, influencing the signal integrity and power integrity of serial link. System level model has been created for USB HSLINK taking into account the external parameters like board, package, measurement environment which influence the performance of the channel. Parameters variations appearing from manufactura-bility constraints, material property constraints, design tolerance etc affecting the serial link performance has been optimized using Taguchi method based on statistical co-analysis. Using the Taguchi statistical techniques, sensitivity analysis on parameter variations affecting HSLINK performance is analyzed and optimized for desired performance.


IEEE Electromagnetic Compatibility Magazine | 2013

Selection and placement of decoupling capacitors in high speed systems

Jai Narayan Tripathi; Jayanta Mukherjee; Prakash R. Apte; Nitin Kumar Chhabra; Raj Kumar Nagpal; Rakesh Malik

The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.


Iete Technical Review | 2012

Signal Integrity and Power Integrity Issues at System Level

Jai Narayan Tripathi; Raj Kumar Nagpal; Rakesh Malik

Abstract System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity violation, stability, causality, and interoperability, are also discussed.


system on chip conference | 2015

Analysis of a serial link for power supply induced jitter

Jai Narayan Tripathi; Hiten Advani; Raj Kumar Nagpal; Vijender Kumar Sharma; Rakesh Malik

An analysis of power supply induced jitter in a high speed serial link is presented in this paper. An equivalent reduced model for serial link is used for the analysis. Jitter induced by the ripples in power delivery network is analyzed by a small signal equivalent model. The effect is modeled by a transfer function which is not technology specific and can be used generically for System-On-Chip (SoC) level design considerations. The analysis is supported by experimental results by simulation in 130nm BiCMoS RF technology and 28nm FDSOI technology (both technologies are of STMicroelectronics).


asia pacific conference on circuits and systems | 2010

Designing Asymmetric 2.4 GHz RF Oscillator for improving Signal Integrity by Design of Experiments

Jai Narayan Tripathi; Jayanta Mukherjee; Prakash R. Apte

Designing of an Asymmetric RF Oscillator for improved Signal Integrity, using Design of Experiments is presented and Taguchi Orthogonal Array is used for the same. Dependence of various physical parameters on output quality parameters that are Eye Height and Jitter, are shown by curves. Jitter is reduced and Eye Height is increased and as outcome of both, Eye SNR is increased. All in all, Designing of an Asymmetric Oscillator for better Signal Integrity is shown using Design of Experiments.

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Jayanta Mukherjee

Indian Institute of Technology Bombay

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Vijender Kumar Sharma

Indraprastha Institute of Information Technology

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Hitesh Shrimali

Indian Institute of Technology Mandi

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Prakash R. Apte

Indian Institutes of Technology

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Sujay Deb

Indraprastha Institute of Information Technology

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