Rakesh Malik

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization

To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found.

A comparative analysis of jitter estimation techniques

With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.

DESIGN OF PLANAR EBG STRUCTURES USING CUCKOO SEARCH ALGORITHM FOR POWER/GROUND NOISE SUPPRESSION

This paper deals with the application of a meta-heuristic optimization algorithm, namely the Cuckoo Search Algorithm in design of the electromagnetic band gap (EBG) structures. These EBG structures are employed for the purpose of suppressing power/ground noise in printed circuit boards. A design example of 2D planar EBG structure in the specifled frequency band is presented and implemented. The measured results are found to be in good agreement with the simulation as well as the analytical results.

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization

Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel and accurate methodology is presented which can be used for any high speed Power delivery Network.

A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits

A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier published structures. Suppression of resonant cavity modes of power plane by EBG structure is also shown. The adoption of EBG structure in power deliver network is recommended to reduce the high frequency noise coupling between neighboring devices. These structures further help in better EMI/EMC compliance of the product by attenuating the propagation of high frequency noise between devices. The EBG structure usage can be on board, package or at die level.

Robust optimization of serial link system for signal integrity and power integrity

Signal Integrity (SI) and Power Integrity (PI) are the most critical issues for higher operational speeds in semiconductor industry. This work identifies and optimizes the parameters of board, package and termination environment, influencing the signal integrity and power integrity of serial link. System level model has been created for USB HSLINK taking into account the external parameters like board, package, measurement environment which influence the performance of the channel. Parameters variations appearing from manufactura-bility constraints, material property constraints, design tolerance etc affecting the serial link performance has been optimized using Taguchi method based on statistical co-analysis. Using the Taguchi statistical techniques, sensitivity analysis on parameter variations affecting HSLINK performance is analyzed and optimized for desired performance.

Selection and placement of decoupling capacitors in high speed systems

The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

Signal Integrity and Power Integrity Issues at System Level

Abstract System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity violation, stability, causality, and interoperability, are also discussed.

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm2 area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM is 0.20 pJ/step.