Jaione Tirapu Azpiroz

Process optimization through model based SRAF printing prediction

Sub-Resolution Assist Features (SRAFs) are used in optical lithography to improve the manufacturing process window (PW). They are added to the mask shapes to create a denser environment that improves the printability of the target design shapes on wafer. As the critical dimensions (CDs) that need to be patterned shrink with every technology generation, SRAFs have become a critical and key component in enabling processes with manufacturable process windows. The size and placement of the SRAFs must be carefully optimized to provide the maximum benefit to the main feature while avoiding any printing on resist that could affect subsequent etching processes. The un-intended printing of assist features on wafer is a critical yield detractor and is especially pervasive in newer technology nodes, where more aggressive and more complex SRAF patterns and placement are becoming commonplace. The need for the accurate prediction of SRAF printing is therefore very important to achieve the maximum main feature process window benefit without any assist feature printing. Traditionally, the optimization of SRAF sizing and placement consisted of a set of rules obtained through the extensive analysis of wafer printability on a variety of assisted mask patterns while using Scanning Electron Microscope images of the resist surface to monitor unwanted SRAF printing. Recent advances in model-based assist feature optimization methods allow for the automated adjustment of both main feature and assist feature size and placement through simulation of the aerial image, but critically rely on the accuracy of the lithography process model to ensure non-printing of the SRAF. Lithography or Optical Proximity Correction (OPC) models usually comprising an optical and a resist model are calibrated to measurements of the resist bottom CD. These models are naturally better at predicting the printing of SRAFS that are lines in resist. When the SRAFs are holes in resist, for eg. assist features supporting main features on a dark field mask, or SRAFs supporting inverse tone features on a bright field mask, these models do not have the required accuracy in predicting SRAF printing. SRAF printability prediction has thus far been tackled by large dose adjustments to the OPC model, to match simulation to wafer results. The drawbacks of this method have been two-fold - simple dose adjustments do not accurately predict printing across various SRAF configurations and the main feature printability is compromised We present in this paper a method to calibrate and predict printing of assist features that appear as a dimpling in the resist surface, by carefully selecting the calibration data and separately tuning the model parameters for the main feature and of the SRAF printing models. With this method, we obtain a model that accurately predicts the printing of various configurations of SRAFs on wafer while still maintaining the accuracy on the main features. An analysis of the implementation of such a model in the OPC flow and the corresponding supporting results will be presented.

Improving yield through the application of process window OPC

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.

Critical impact of mask electromagnetic effects on optical proximity corrections performance for 45nm and beyond

Numerous studies have addressed the challenges ahead in optical lithography due to electromagnetic effects in photomasks (so-called emf effects), which arise from the complex interaction of the illumination with mask topography whose size now approaches the wavelength. As design critical dimensions shrink, the electromagnetic response of the reticle becomes a complicated function of the incident polarization with serious impact to printed critical dimension (CD) on the wafer. A number of modeling techniques are available to approximately account for emf in the process models employed during optical proximity correction calculations, with small to moderate runtime penalty. Among them are simple mask CD bias, the boundary layer [J. T. Azpiroz et al., Proc. SPIE 5040, 1611 (2003)], the domain decomposition method [K. Adam and A. Neureuther, Proc. SPIE 4562, 1051 (2001)], and techniques based on the geometrical theory of diffraction [G. K. Chua et al., Proc. SPIE 5377, 1267 (2004); A. Khoh et al., J. Opt. Soc...

Wafer Plane Inspection Evaluated for Photomask Production

Wafer Plane Inspection (WPI) is a novel approach to inspection, developed to enable high inspectability on fragmented mask features at the optimal defect sensitivity. It builds on well-established high resolution inspection capabilities to complement existing manufacturing methods. The production of defect-free photomasks is practical today only because of informed decisions on the impact of defects identified. The defect size, location and its measured printing impact can dictate that a mask is perfectly good for lithographic purposes. This inspection - verification - repair loop is timeconsuming and is predicated on the fact that detectable photomask defects do not always resolve or matter on wafer. This paper will introduce and evaluate an alternative approach that moves the mask inspection to the wafer plane. WPI uses a high NA inspection of the mask to construct a physical mask model. This mask model is used to create the mask image in the wafer plane. Finally, a threshold model is applied to enhance sensitivity to printing defects. WPI essentially eliminates the non-printing inspection stops and relaxes some of the pattern restrictions currently placed on incoming photomask designs. This paper outlines the WPI technology and explores its application to patterns and substrates representative of 32nm designs. The implications of deploying Wafer Plane Inspection will be discussed.

Radiometric consistency in source specifications for lithography

There is a surprising lack of clarity about the exact quantity that a lithographic source map should specify. Under the plausible interpretation that input source maps should tabulate radiance, one will find with standard imaging codes that simulated wafer plane source intensities appear to violate the brightness theorem. The apparent deviation (a cosine factor in the illumination pupil) represents one of many obliquity/inclination factors involved in propagation through the imaging system whose interpretation in the literature is often somewhat obscure, but which have become numerically significant in todays hyper-NA OPC applications. We show that the seeming brightness distortion in the illumination pupil arises because the customary direction-cosine gridding of this aperture yields non-uniform solid-angle subtense in the source pixels. Once the appropriate solid angle factor is included, each entry in the source map becomes proportional to the total |E|^2 that the associated pixel produces on the mask. This quantitative definition of lithographic source distributions is consistent with the plane-wave spectrum approach adopted by litho simulators, in that these simulators essentially propagate |E|^2 along the interfering diffraction orders from the mask input to the resist film. It can be shown using either the rigorous Franz formulation of vector diffraction theory, or an angular spectrum approach, that such an |E|^2 plane-wave weighting will provide the standard inclination factor if the source elements are incoherent and the mask model is accurate. This inclination factor is usually derived from a classical Rayleigh-Sommerfeld diffraction integral, and we show that the nominally discrepant inclination factors used by the various diffraction integrals of this class can all be made to yield the same result as the Franz formula when rigorous mask simulation is employed, and further that these cosine factors have a simple geometrical interpretation. On this basis one can then obtain for the lens as a whole the standard mask-to-wafer obliquity factor used by litho simulators. This obliquity factor is shown to express the brightness invariance theorem, making the simulators output consistent with the brightness theorem if the source map tabulates the product of radiance and pixel solid angle, as our source definition specifies. We show by experiment that dose-to-clear data can be modeled more accurately when the correct obliquity factor is used.

SMO Photomask Inspection in the Lithographic Plane

Source Mask Optimization (SMO) describes the co-optimization of the illumination source and mask pattern in the frequency domain. While some restrictions for manufacturable sources and masks are included in the process, the resulting photomasks do not resemble the initial designs. Some common features of SMO masks are that the line edges are heavily fragmented, the minimum design features are small and there is no one-to-one correspondence between design and mask features. When it is not possible to link a single mask feature directly to its resist counterpart, traditional concepts of mask defects no longer apply and photomask inspection emerges as a significant challenge. Aerial Plane Inspection (API) is a lithographic inspection mode that moves the detection of defects to the lithographic plane. They can be deployed to study the lithographic impact of SMO mask defects. This paper briefly reviews SMO and the lithography inspection technologies and explores their applicability to 22nm designs by presenting SMO mask inspection results. These results are compared to simulated wafer print expectations.

Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: An Integrated Approach to Design for Manufacturing (DFM)

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

Impact of sub-wavelength electromagnetic diffraction in optical lithography for semiconductor chip manufacturing

Despite many challenges, optical lithography continues to enable an exponential decrease in the dimensions of circuit patterns that are printed in high volume in advanced microelectronics. The laser wavelength used to power the lithographic system has not scaled as fast, constraining these systems to operate with 193nm wavelength while printing features less than one-fourth that size. In this paper we explore the mechanism in which sub-resolution diffraction at the lithographic photo-mask translates into severe shifts in focus of the patterns transferred to the wafer in a pattern-dependent manner and their dependency on several parameters of the lithography process.

Isotropic treatment of EMF effects in advanced photomasks

Classical methods for modeling electromagnetic scattering from the topography of lithographic reticles must place a high premium on fast computation, and toward that end they apply pre-stored perturbations (e.g. the so-called boundary layers) to feature edges in order to approximate the impact of finite-thickness mask films. Though approximate, these methods involve E&M calculations with vector fields, and so employ edge-field corrections that are different for edges oriented parallel or perpendicular to the vector field. As a result these methods entail a requirement for two separate aerial image simulations using orthogonal source polarizations in order to represent unpolarized illumination. This imposes a minimum 2X runtime penalty relative to baseline thin-mask (TMA) simulations, since the known method for combining the effect of both polarizations into one single set of imaging TCCs applies only to thin-mask calculations. More severe performance penalties are common in so-called sparse imaging methodologies when topographic effects are included, since the separated treatment of feature edges and the internal area of the features can increase the number of memory lookups required. In this paper an isotropic field perturbation approach is evaluated, in which an isotropic edge field correction, common to all edge orientations, mimics the effect of the true parallel and perpendicular edge field perturbations when the mask is illuminated with unpolarized light, as well as in certain cases of polarized illumination. The isofield is not an ad hoc empirical correction but rather an accurate approximation in the limit of modest departures from scalar TMA. More specifically, we show that the isofield model accounts for vector imaging effects with full accuracy in the TMA terms, and in an approximate way in the electromagnetic edge-field terms that becomes accurate when the polarization dependence of the TMA terms is small. We will show with comparison to more rigorous electromagnetic models and simulations, as well as against wafer measurements that the accuracy loss relative to classic polarized EMF correction approach is within a small percentage on mask blanks where the electromagnetic edge field perturbation terms are small relative to the TMA term. Methodology to extend these models into the subwavelength diffraction regime will be discussed.

Graphene-enabled and directed nanomaterial placement from solution for large-scale device integration

Directed placement of solution-based nanomaterials at predefined locations with nanoscale precision limits bottom-up integration in semiconductor process technology. We report a method for electric-field-assisted placement of nanomaterials from solution by means of large-scale graphene layers featuring nanoscale deposition sites. The structured graphene layers are prepared via either transfer or synthesis on standard substrates, and then are removed once nanomaterial deposition is completed, yielding material assemblies with nanoscale resolution that cover surface areas >1 mm2. In order to demonstrate the broad applicability, we have assembled representative zero-dimensional, one-dimensional, and two-dimensional semiconductors at predefined substrate locations and integrated them into nanoelectronic devices. Ultimately, this method opens a route to bottom-up integration of nanomaterials for industry-scale applications.The placement of nanomaterials at predefined locations is a key requirement for their integration in nanoelectronic devices. Here, the authors devise a method allowing placement of solution-based nanomaterials by using structured graphene layers as deposition sites with the aid of an electric field.